Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (register, lsl, 64-bit)

Test 1: uops

Code:

  cmn x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100470950061100030425200020001000408770709709498253561100010002000709781110011000000073122116842000710710710710710
100470950061100030425200020001000408770709709498213561100010002000709781110011000000073122116842000710710710710710
100470950061100030425200020001000408770709709498253561100010002000709781110011000000073122116842000710710710710710
100470950061100030425200020001000408770709709498213561100010002000709781110011000000073122116842000710710710710710
100470960061100030425200020001000408770709709498213561100010002000709781110011000000073122116842000710710710710710
100470950061100030425200020001000408770709709498213561100010002000709781110011000000073122116842000710710710710710
100470950061100030425200020001000408770709709498253561100010002000709781110011000000073122116842000710710710710710
100470960061100030425200020001000408770709709498213561100010002000709781110011000000073122116842000710710710710710
100470950061100030425200020001000408770709709498213561100010002000709781110011000000073122116842000710710710710710
100470950061100030425200020001000408770709709498253561100010002000709781110011000000073122116842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, x1, lsl #17
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100100013101231222995430000101003003630036300363003630036
202043003522500631100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100200013101231222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100300013101231222995430000101003003630036300363003630218
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100100013101231222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100300013101231222995430000101003003630036300363003630036
20204300352240061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100100013101231222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100200013101231222995430000101003003630036300363003630036
20204300352250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100100013101231222995430000101003003630036300363003630036
20204300802250061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100100013101231222995430000101003003630036300363003630036
20204300352240061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100100013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
200243003522500611000029891253001030010200101956289004926955030035300352739132749820010200203002030035145112002110910200101001000000127013311299583000000100103003630036300363003630036
200243003522400611000029891253001030010200101956289004926955030035300352739132749820010200203002030035145112002110910200101001003000127013321299583000000100103003630036300363003630036
2002430035225005361000029891253001030010200101956289004926955030035300352739132749820010200203002030035145112002110910200101001002000127013311299583000000100103003630036300363003630036
2002430035225006110000298912530010300102001019562890049269550300353003527391327498200102002030020300351451120021109102001010010041600127013311299583000000100103003630036300363003630036
2002430035225006110000298912530010300102001019562890049269550300353003527391327498200102002030020300351451120021109102001010010018100127013311299583000000100103003630036300363003630036
200243003522500611000029891253001030010200101956289004926955330035300352739132749820010200203002030035145112002110910200101001000000127013311299583000000100103003630036300363003630036
200243003522500611000029891253001030010200101956289004926955030035300352739132749820010200203002030035145112002110910200101001000000127013311299583000000100103003630036300363003630036
200243003522500611000029891253001030010200101956289004926955030035300352739132749820010200203002030035145112002110910200101001000000127013311299583000000100103003630036300363003630036
200243003522500611000029891253001030010200101956289004926955030035300352739132749820010200203002030035145112002110910200101001001300127013311299583000000100103003630036300363003630036
20024300352250157471000029891253001030010200101956289004926955030035300352739132749820010200203002030035145112002110910200101001000000127013311299583000000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, x1, lsl #17
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013100231222995430000101003003630036300363003630036
2020430035225006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013100231222995430000101003003630036300363003630036
2020430035225006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500122710000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101331222995430000101003003630036300363003630036
202043003522500103410000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010030013101231222995430000101003003630036300363003630036
202043003522500133310000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352240611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100002121270233112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010000001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010000031270133112995830000100103003630036300363003630036
20024300352250536100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010030031270133112995830000100103003630036300363003630036
20024300352250536100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001001270133112995830000100103003630036300363003630036
20024300352250251100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010000001270133112995830022100103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010000001270133112995830000100103003630036300363003630036
20024300352250245100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010000001270133112995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmn x0, x1, lsl #17
  cmn x0, x1, lsl #17
  cmn x0, x1, lsl #17
  cmn x0, x1, lsl #17
  cmn x0, x1, lsl #17
  cmn x0, x1, lsl #17
  cmn x0, x1, lsl #17
  cmn x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045345540000000000618000048741251601001601008010034400051495033053410534104329820503433608010080200160200534107811802011009910080100100000511042432533921600001005341153411534115341153411
802045341040000000000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511022422533921600001005341153411534115341153411
802045341040000000000618000048741251601001601008010034400051495033053410534104329820603433608010080200160200534107811802011009910080100100000511022422533921600001005341153411534115341153411
802045341040000000000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511022422533921600001005341153411534115341153411
802045341040000000000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100020511022422533921601081005341153411534645357653411
8020453410400010011120618000048741251601001601008010034400051495033053410534104329820603433608010080200160200534107811802011009910080100100303511022422533921600001005341153411534115341153411
80204534104000000001207688000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511022422533921600001005341153411534115341153411
8020453410400000000001038000048741251601001601008010034400051495044253410534104329820803433928042680200160850534647811802011009910080100100103511022422533921600001005341153411534115341153411
802045341040000000000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511022422533921600001005341153411534115341153411
80204534104000000000010298000048741251601001601008010034400051495033053410534104329820503433608010080200160200534107811802011009910080100100000511032422533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800245340239908280000479462516001016001080010343813014950300053380533804329027073433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
8002453380400072680000479462516001016001080010343813004950300053380533804329025623433528001080020160020533807811800211091080010102050201241153402160000105338153381533815338153381
800245338040006180000479462516001016001080010343813014950300053380533804329027073433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
800245338040006180000479462516001016001080010343813004950300053380533804329027073433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
800245338040006180000479462516001016001080010343813004950300053380533804329025623433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
800245338040006180000479462516001016001080010343813004950300053380533804329025623433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
8002453380399015380000479462516001016001080010343813004950300053380533804329027073433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
800245338040006180000479462516001016001080010343813004950300053380533804329027073433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
800245338040006180000479462516001016001080010343813004950300053380533804329027073433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381
800245338039906180000479462516001016001080010343813014950300053380533804329025623433528001080020160020533807811800211091080010100050201241153359160000105338153381533815338153381