Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORN (register, lsl, 32-bit)

Test 1: uops

Code:

  orn w0, w0, w1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203515000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203515000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203515000061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  orn w0, w0, w1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515500020810000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036
102042003515500010310000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100010710259221979120000101002003620036200362003620036
102042003515500044010000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036
10204200351560006110000198032520100201001010018534204916955200352003518429318716101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036
102042003515500035810000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036
10204200351550006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036
102042003515500016610000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036
102042003515600029610000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036
102042003515500126110000198032520100201001010018534204917000200352003518429318700101001020020200200354211102011009910010100100010710259221979120000101002003620036200362003620036
10204200351550006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000710259221979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515506610000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
1002420035155016010000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
100242003515606110000197432520010200101016518531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
100242003515506110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
100242003515506110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
100242003515506110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101003640363331979220000100102003620036200362003620036
100242003515606110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
1002420035155010310000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
100242003515566110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036
100242003515536110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000640363331979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  orn w0, w1, w0, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515600000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000000710297242003420080101002035820351203572031320359
10204203061581777926164837100901980821120345202931130019957714917367204462045518444451885811597117172318820445421111020110099100101001000219260709192161222011820164101002049520497204932054220532
10204204961590101013208803253100811981923120394203681160020019114917413204912049218442531887510100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
1020420035161000301321101000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515000000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515000000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515000000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000300710159111979120000101002003620036200362003620036
1020420035150000002571000019803252010020100101001853421491695520035200351842931870010100102002020020078421110201100991001010010000000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03181e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351550006891000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
1002420035155001761661000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351550002791000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515500011951000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515500010531000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351550002291000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100200640263221979220000100102003620036200362003620036
100242003515500012241000019743252001020010100101859914916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
1002420035155000821000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351550007531000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351550001461000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  orn w0, w8, w9, lsl #17
  orn w1, w8, w9, lsl #17
  orn w2, w8, w9, lsl #17
  orn w3, w8, w9, lsl #17
  orn w4, w8, w9, lsl #17
  orn w5, w8, w9, lsl #17
  orn w6, w8, w9, lsl #17
  orn w7, w8, w9, lsl #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267692070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051104221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626791267862684626726
80204267252070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726
802042672520700044180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726
802042672520700216180000260942516010016010080100164318149236452672526725166153166778045280200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726
80204267252070006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000051101221126717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426717207334680000212802516001016001080010163142492363126711267111662331668580010800201600202671139118002110910800101000502011226926704160000800102671226712267122671226712
8002426711207061800002128025160010160010800101631424923631267112671116623316685800108002016002026711391180021109108001010005020112210526704160000800102671226712267122671226712
80024267112070618000021280251600101600108001016314249236312671126711166233166858022080020160020267113911800211091080010100050204228926820160000800102671226712267122676826712
80024267112060618000021280251600101600108001016314249236312671126711166233166858001080020160020267113911800211091080010100050206225426704160000800102671226712267122671226712
800242671120706180000212802516001016001080010163142492363126711267111662331668580010800201600202671139118002110910800101000502042251126704160000800102671226712267122671226712
8002426711207126180000212802516001016001080010163142492363126711267111662331668580010800201600202671139118002110910800101000502052251026704160000800102671226712267122671226712
8002426711207061800002128025160010160010800101631424923631267112671116623316685800108002016002026711391180021109108001010005020112211626704160000800102671226712267122671226712
800242671120702928000021280251600101600108001016314249236312671126711166233166858001080020160020267113911800211091080010100050206226726704160000800102671226712267122671226712
80024267112070618000021280251600101600108001016314249236312671126711166233166858001080020160020267113911800211091080010100050205225626704160000800102671226712267122671226712
800242671120706180000212802516001016001080010163142492363126711267111662331668580010800201600202671139118002110910800101000502032251126704160000800102671226712267122671226712