Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSBB

Test 1: uops

Code:

  ssbb

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)6066696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)st unit uop (a7)l1d cache writeback (a8)acbccfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
40042702820301000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820201000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820201000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820301000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820201000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
400427028203301000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820201000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820301000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820201000270132202510001000100050591260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029
40042702820301000270132202510001000100050001260004923948270282702826000326010100010002702827028111001200001000100073116112700010002702927029270292702927029

Test 2: throughput

Code:

  ssbb

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 27.0135

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fst unit uop (a7)l1d cache writeback (a8)a9acbcc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4020427018720240000010000270120220124101001001000010010000500500001260099492670552701352701352600993260117101002001000020027016421609511102011009910010010020000001000010000000071001171127010610000100270136270136270136270136270136
4020427013520240000010000270120220124101001001000010010000500500001260099492670552701352701352600993260117101002001000420027013521609511102011009910010010020000301000010000000071001171127010610000100270136270136270136270136270136
4020427013520230000010000270120220124101001001000010010000500500000260099492670552701352701352600993260117101002001000020027016421609511102011009910010010020000001000010000000071001171127010610000100270136270136270136270136270136
4020427013520240000010000270120220124101001001000010010000500500001260099492670552701352701352600993260117101002001000020027013521609521102011009910010010020000001000010000000071001171127010610000100270136270325270136270136270163
4020427013520230000010000270120220124101001001000010010000500500001260099492670552701352701352600993260117101002001000020027013521609511102011009910010010020000001000010000000071001171127010610000100270136270136270136270136270136
4020427013520240000010000270120220124101001001000010010000500500001260099492670552701352701352600993260117101002001000020027013521609511102011009910010010020000001000010000000071001171127010610000100270136270136270136270136270136
4020427013520230000010000270120220124101001001000010010000500500000260099492670552701352701352600993260117101002001000020027016421609511102011009910010010020000001000010000000071001171127010610000100270136270136270136270136270136
4020427013520240000010000270120220124101001001000010010000500500101260099492670552701352701352600993260134101002001000020027013521609511102011009910010010020000001000010000000171001171127010610000100270136270136270136270136270136
4020427013520240012010000270120220124101001001000010010000500500001260099492670552701352701352600993260117101002001000020027013521609511102011009910010010020000001000010000000071001171127010610000100270136270136270136270165270136
402042701352023000065110000270120220124101001001000010010000500500001260099492670552701352701352600993260117101002001000020027013521609511102011009910010010020000001000010000000071001171127010610000100270136270136270136270136270136

1000 unrolls and 10 iterations

Result (median cycles for code): 27.0045

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbcbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4002427006120230100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010020000010000100000640317322700161000010270046270046270046270046270046
4002427004520220100002700302200341001010100001010000505000002600094926696532700452700452600093260027100102010000202700452700451110021109101010020000010000100000640217222700161000010270046270046270046270046270046
4002427004520240100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010020000410009100000640217322700161000010270046270046270046270046270046
4002427004520230100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010020000010000100000640317332700161000010270046270046270046270046270046
4002427004520230100002700302200341001010100001010000505000002600304926696502700452700452600093260027100102010000202700452700451110021109101010020000010012100000640217222700161000010270046270046270046270046270046
4002427004520220100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010020000010003100000640317222700161000010270046270046270046270046270046
4002427004520220100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010020000010000100000640217332700161000010270046270046270046270046270046
4002427004520230100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010020000010000100000640317332700161000010270046270046270046270046270046
4002427007420220100002700302200341001010100001010000505000012600094926696502700452700452600099260027100102010000202700452700451110021109101010020000010000100000640217322700421000010270046270046270046270046270046
4002427004520239100002701102200341001010100001010000505013512600094926696502700452700452600093260027100192010002202710602706996110021109101010020000110003100000666217322700161000010270046270046270046270046270046