Firestorm: ORN (register, lsr, 64-bit) measurements

Code:

  orn x0, x0, x1, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	0	0	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	12	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	2	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	0	0	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	3	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	0	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1846	1000	1000	2000	2035	42	1	1	1001	1000	0	73	2	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	0	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	0	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	0	0	0	139	1009	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	0	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	0	3	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  orn x0, x0, x1, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	2	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	1	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	2	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	27	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	365	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	149	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	170	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	3	0	1	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	149	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	124	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	191	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	1	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	124	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18496	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  orn x0, x1, x0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	155	2	0	103	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	3	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	12	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	155	0	0	0	0	6	0	0	628	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	44	1	1	10021	10	9	10	10010	10	0	0	0	2	0	0	0	0	642	7	63	4	3	19792	20000	10010	20036	20036	20036	20171	20173
10024	20035	157	0	0	0	0	0	0	1	252	10000	19743	25	20010	20010	10012	187039	1	49	16955	20035	20035	18451	3	18718	10010	10020	20360	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	1	0	0	0	640	3	63	3	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	0	0	3	0	9	0	0	61	10000	19743	25	20010	20012	10012	185310	1	49	16955	20035	20035	18453	3	18718	10012	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	3	63	3	3	19792	20068	10010	20036	20036	20036	20036	20036
10024	20171	156	0	0	0	3	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18453	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	3	63	3	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	0	0	3	0	12	0	0	61	10009	19743	25	20012	20012	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20068	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	704	3	63	3	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18453	3	18722	10012	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	3	63	3	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	0	0	0	0	270	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10012	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	2	0	0	0	0	0	0	0	640	3	59	3	3	19792	20000	10010	20036	20036	20172	20036	20036
10024	20035	155	0	0	0	0	15	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	165	0	640	3	63	3	3	19792	20000	10010	20081	20036	20036	20036	20036
10024	20035	155	0	0	0	0	0	0	0	61	10036	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20171	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	3	63	6	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	0	0	0	0	0	0	0	2330	10000	19741	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18722	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	642	7	63	3	3	19792	20000	10010	20036	20036	20081	20036	20036

Test 4: throughput

Count: 8

Code:

  orn x0, x8, x9, lsr #17
  orn x1, x8, x9, lsr #17
  orn x2, x8, x9, lsr #17
  orn x3, x8, x9, lsr #17
  orn x4, x8, x9, lsr #17
  orn x5, x8, x9, lsr #17
  orn x6, x8, x9, lsr #17
  orn x7, x8, x9, lsr #17

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80204	26769	208	1	1	12	0	3	69	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5116	11	22	9	9	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	0	0	3	69	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5116	4	22	9	9	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	0	0	3	69	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	1	0	0	5116	9	22	9	9	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	0	264	3	69	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	9	5116	10	22	5	10	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	208	1	1	0	0	3	111	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	11	0	5116	9	22	4	9	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	0	0	3	111	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5116	9	22	7	7	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	12	0	3	69	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16617	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	1	0	0	5116	9	22	9	4	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	0	0	3	69	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5116	9	22	9	9	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	0	0	3	69	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5116	9	22	9	9	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	1	1	0	0	3	69	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	1	0	0	5116	9	22	10	10	26717	160000	0	80100	26726	26726	26726	26726	26726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	26717	215	0	0	0	0	0	0	0	5	82	80000	21280	25	160010	160010	80010	163142	1	3	49	23631	26711	26711	16623	0	6	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	9	22	6	17	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	246	108	1	61	80000	21280	25	160010	160010	80010	163142	1	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	16	22	9	18	26704	160000	0	80010	27163	27577	27345	27520	27513
80024	27348	219	2	0	0	15	11	1980	616	0	3224	81159	19063	194	162576	162021	82108	212818	1	0	49	24323	27521	27524	16641	0	115	17000	83166	81968	166510	27569	39	12	1	80021	10	9	10	80010	10	0	0	0	6480	0	5976	3	18	81	20	8	27214	161815	0	80010	27405	27171	27464	27294	27291
80024	27350	213	4	4	0	16	13	1452	968	0	3202	81115	17624	315	162406	162774	82324	212789	1	0	49	24267	27633	27520	16642	0	93	17024	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	4	2	2	8900	0	5190	0	16	22	6	17	26704	162385	0	80010	26712	26884	26943	27175	27516
80024	26998	209	0	2	1	7	11	924	968	0	229	80240	21930	25	160010	162402	80642	163142	1	0	49	23631	26711	26711	16627	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	17	22	17	8	26704	160000	0	80010	26712	26712	26712	26712	26764
80024	26711	200	0	0	0	0	0	0	0	0	191	80000	21280	25	160010	160010	80010	163142	1	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	6	22	8	17	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	1	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	17	22	17	17	26704	160000	17	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	1	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	6	22	6	17	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	1	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	6	22	8	17	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	1	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	6	22	17	17	26704	160000	0	80010	26712	26712	26712	26712	26712

ORN (register, lsr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations