Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STCLRLH

Test 1: uops

Code:

  stclrlh w0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.007

Integer unit issues: 1.007

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e1f223a3f4951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)79map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
7300534153255119119100100710532433950021985300810062000100020001117016946849310280337423411431030000100020002000400033938267311710011000100002003300100710010162006513222149261072828084356011572415836044441165752329481007191071688517672200010003398734087341383403034147
7300434062254117122100100611537733953021939300810082000100020001103817061549309900337673402331030000100020002000400034062264611710011000100002002320100510011282006312321150131060727969358314572415635404437145654329731004190121689317650200010003413034084340773406034061
73004341412541151191001007115312339770219843007100320001000200011075168428493105903370734036310300001000200020004000340102693117100110001000020052231009100512112004710322149281053617938355012562416035634440204649329661005189881666917416200010003404634103340153403234151
7300434104255124119100101910532433940121989300810072000100020001103116938549310100337273411531030000100020002000400034039265311710011000100002003333100710013082005710222150061065817947354111562416235804449204757329681008190931670017529200010003398134137340383409334089
730043411625511811610010091053473391412206430071007200010002000110391706414930997033661339933103000010002000200040003406827271171001100010000200440210081001218200441002215054106162798235639482414535634440145144330321004188271680417776200010003399934032339843400834087
7300434064254121118100101310529133913022128300810082000100020001102616978549310340336983401331030000100020002000400033988268211710011000100002004320100510013162005412222150011073527950356511512417935684443135055330121006187161690217724200010003413034080341273409134104
730043407925612111710010101052513386202206430081008200010002000109761701164930997033694340043103000010002000200040003402726641171001100010000200442310081001026200591202114922106672795735799522417235914446154858330491008190601692217619200010003403634100340993414034203
73004341372551181131001006105422339620219733008100620001000200011023170094493102003380734061310300001000200020004000339902665117100110001000020035221005100501112003612022148861067027961353715492422536774442144845329631007191331660717522200010003399134065340863417134124
73004341352551151190001010105323338770220873005100720001000200011066170527493094103366934071310300001000200020004000339982651117100110001000020024001007100122122006510222150161061847966356511442422536134452175251330011007189691686217622200010003407534123341313410734176
7300434196254122022111100911541233952022114300810072000100020001112917061449309420336993412631230000100020002000400033947265411710011000100002002322100710014262006710222150541078018001353710542418736084442116050330621007189541688517428200010003400134087341363411734141

Test 2: throughput

Code:

  stclrlh w0, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0074

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2022233a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4020670074525101000050579421027070058350131657412254038920338200002010020000204438133205521194496699307003370073645111765033401002020020000302004000070073711120201100991001000010100100001100200481613859198681011010010012520292007113410521351411310117116986120211131320000201007007570075700757007570075
4020470074524202000050729501020070059300141257999254036420347200002010020000204527933214650119496699407003870074645123650314010020200200003020040000700737111202011009910010000101001000011002005516995819872100681001112272858200701351137155142131011611698612026401320000201007008570074700757007570074
402047007352522200005065940102107005838115115791625403932038720000201002000020447513320972110849669940700387007464512365032401002020020000302004000070073701120201100991001000010100100001100200571713747198721006510009145832532006113610471571521310116116986120214131320000201007007470074700757007570074
4020470073525222000050619331015070059381101757642254039920378200002010020000204439233206831127496699407003870074645123650324010020200200003020040000700737111202011009910010000101001000011002009519172561987210077100104463050200891349421731431330116116986020453131320000201007007570075700747007470075
40204700745252010000505493810160700593711319567622540338203052000020100200002044182332089211834966994070033700736451136503240100202002000030200400007007470112020110099100100001010010000110020045171565319872100731001120374053200681389391001521310116116986020256131320000201007007470075700757007570075
40204700735242220000506293910230700594111313576232540324204022000020100200002044715332072311254966994070038700746451236503240100202002000030200400007007371112020110099100100001010010000110020050171365919872100601001120492462200581409452101501310116116986120463131320000201007007570075700757007470075
40204700745252020000507494010182870059491131356704254037520268200002010020000204452833203631172496699307003370073645113650324010020200200003020040000700747011202011009910010000101001000011002004817101481987210078100101228246220057132104115715213101161169860204400020000201007007570075700747007470075
4020470074525222000050711044102207005929113175771725403632034120000201002000020447823321057110549669940700427007464512365032401002020020000302004000070073701120201100991001000010100100001100200511919371198721008410011043712622008014411551741521310116116986120318131320000201007007570075700757007470075
402047007452522200005071943102307005844116125754325402752048620000201002000020451693320695022349669940700387007464512365031401002020020000302004000070073701120201100991001000010100100001100200711615553198721006410012123918522008113810441561421310116116986120484131320000201007007570074700747007470075
4020470074524220000050611034101836700593111914571242540546204142000020100200002044806332121412094966994070033700566451236503140100202002000030200400007007470112020110099100100001010010000110020041262742019886100481000850302855200701389451021411310116116986020191131320000201007007670074700747007470075

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f20222324293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40026700695250000100505314410008070054415101457880254028620217200002001020000204417333200320128496698907003370069645293650474001000200202000030020400007006963112002110910100001001010000010200242421962198711004410002000047200321212396000001270216226985620192101020000200107007070070700707007070070
40024700695250020000508436410001136700352052612570242540233202202000020010200002044882332146302374966989070033700696452936504940010002002020000300204000070067631120021109101000010010100000102002307350198711007110002113526332005112313223500001270216226985620448101020000200107007070070700687007070070
4002470069525002000050422241000130700522241216579692540520201992000020010200002044494332193511114966989070033700696452736504940010002002020000300204000070069571120021109101000010010100000102002401135519871100511000221366422004912934394000012702162269856205300020000200107007070070700707006870070
40024700695250000000504612810007070054245101058343254016820219200002001020000204354433211830129496698907003170064645293650304001000200202000030020400007006963112002110910100001001010000010200220734619871100651000201371828200441252321280000127021622698562031111020000200107007070070701227007370120
40024700675500000000505432410001207003521713105864225402922016820000200102000020444293321934020149669890700337005064529365049400100020020200003002040000700696311200211091010000100101000001020033012855198711005410003000323420038123331920000127031632698372030511020000200107012370070700707007070065
4002470069525000100050922291000120700542352114582112540346203392000020010200002044578332175616849669890700337006964529365049400100020020200003002040000700695711200211091010000100101000011020030011052198711005710011213526352005902633411400001270216226985420290101020000200107007070070700517007070070
4002470069524000000050493381000110700542051611587682540356203552000020010200002044210332153011054966970070033700696452936504940010002002020000300204000070067631120021109101000010010100000102003401304619866100581001011482625200531101309300001270216226985620508101020000200107007070070700707007070068
40024700675250000100505013710001107005425512115749725403862026020000200102000020442863321934111349669890700337006964529365030400100020020200003002040000700696311200211091010000100101000001020033011039198711006910002203422352004712023710900001270216226985620520101020000200107005170070700707007070071
4002470069525022000050642211000120700352751711574412540206202732000020010200002044210332164511484966989070033700696452936503040010002002020000300204000070069571120021109101000010010100000102002801135119866100561000231480512004612535015900001270216226985620327101020000200107007070070700707012270068
40024700675250020000505222010008070054237111058011374022720287200002001020138204557433204641114496698707003370069645293650494001000200202000030020400007006963112002110910100001001010000010200390934519871100561000720316232005512133311200001270216226985620583101020000200107007070070700687007070068

Test 3: throughput

Code:

  stclrlh w0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0133

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3020522019517261001103127569151002222994891023131513265752332178257471184523054965953412648414098849267990270023270087261078413258427398512437193712098231482407847406244287982451102011009910010000100100001100237092261829475122323425260339678174590192700111768965631610219412148271626602000010100220114220106220090220146220156
302042209091731000000002741611001221765410820228867504612673623488101002000084425441052328104074921762222011722015121543911216321301002264201610203200902046240178220137944311020115179910010000100100000100200802128352671810014601735337441174611519242601117221108621702219457231268296002000010100220122220174220146220118222824
302042201171671000000002698810101220084713020191125503862773923248101002000085350521052423605264921703722013322012121538162163263010017651660102002000020200400002201298641110201100991001000010010000010020057001726959100011016978365991735912531001117179808016002194811722802601302000010100220131220119220115220097220145
302042201281649111100002717915000022010408920237125498632710823259101002000085543991052592515154921706522011522013521539962163123010018241978102002000020200400002201259262110201100991001000010010000010020000030262720410000001917437164174530100001117221108622522219361143277376602000010100220138220124220128220136220168
30204220109164800000000271101001122009827720247725506942746723100101002000084076921052451815424921706922013922014721539562163203010015961834102002000020200400002201138121110201100991001000010010000110020000631252744110001001722537289169951183000111722107082252221945224227563101002000010100220142220156220104220100220100
302042201151649000000002716500011220104160202217255046327056231721010020000849989810525072146749217035220129220129215475621634830100167820881020020000202004000022011188411102011009910010000100100000100200000271827378100000017088370501754711527001117221073922423219438186280126602000010100220128220118220134220096220106
30205220103164800000000273271000022012621410202443255060927379229441010020000845667910523979146549217013220099220121215407621635830100182117061020020000202004000022015790811102011009910010000100100000100200000271527375100000016458369181719811327001117221125322522219406146277276602000010100220120220115220161220179220160
302042201451648000000002750300101220102110920188134507602788922676101002000086743381052507215344921707722013322014321548062163333010019661488102002000020200400002201478461110201100991001000010010000010020000027202723610001001708636998172041026001117221030222422219448188277216602000010100220114220128220128220108220154
30204220129164900000000266071000222010819720210325506142744823011101002000085769141052507104714921704722016122011321543362163223010022582125102002000020200400002201139041110201100991001000010010000010020000029192724110000001701237481174841203000111722106402252221946723227645101002000010100220132220114220162220150220134
3020422012516490000000028354150010220100477202426255059727587229671010020000870354710526383153249217051220135220139215419621632730100182515701020320005202064000922013989311102011009910010000100100000100200000272027216100010016617370401724511727001117161104001600219421135276126002000010100220144220146220178220152220161

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0269

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
30025220192164911100003188214100220248901720103025529593288320171100102000010664807105277621141649217198022031422027621545432165523001014715510020200002002040000220236656111002110957481101000010100000102002626334131504100150021555415682156215282226106401526321622219397432842992000010010220257220255220180220288220271
3002422023516501100000315061400122029491802017102552868328642008110010200001061163410526476013944921716102202502202682154283216523300101491341002020000200204081922024872711100211093492210100001010000010200272704231428100160121432414392135814283426106401525821622219388032897992000010010220267220315220318220267220238
3002422023616501000000315011500122025701702014802552942327832009910010200001060968910525649114054921715502202822202162153993216448300101571601002020000200204000022024773711100211094403710100001010000010200252633031468100150121483415042144016263326206401529521622219402032929092000010010220255220313220297220277220269
300242202931650111000031493150022202349002013182552782328792006510010200001065097810525323113274921714802202422202482153803216474300101251181002020000200204000022025266711100211094236010100001010000010200282600315631001662121640416222161714282426006401525821522219417032901902000010010220253220239220241220239220211
300242202551651100000031486150032201759171720113125529543284820069100602000010694015105223531133449217168022032222028521542615216493300101401511002020000200204000022019969811100211096506910100001010000010200252504231554100160221566415562156115282626006401527221622219348132763092000010010220283220259220224220182220247
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