Firestorm: STLXR (64-bit) measurements

Code:

  stlxr w0, x1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 50.674

Integer unit issues: 0.000

Load/store unit issues: 50.674

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	22	3a	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	64	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	37993	285	7	6	1998	1	0	37978	0	7267	50706	50680	87814	1003129	1	1000	49	34913	37993	37993	13140	5937	24394	87814	91431	182864	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44997	5	0	2002	44965	1000	1000	16607	27	2062	30	29	37909	1000	37994	37994	37994	37994	38000
1004	37995	284	7	7	1998	0	0	37978	0	7267	50710	50676	87814	1003114	1	1000	49	34913	37993	37993	13140	5941	24396	87814	91431	182862	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44965	46	0	2001	44965	1000	1000	16607	31	2060	31	31	37909	1000	37994	37994	37994	37994	38001
1004	37993	284	7	7	1998	0	0	37978	0	7267	50674	50683	87844	1003114	0	1000	49	34913	37993	37993	13140	5945	24406	87814	91432	182864	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44981	7	0	2007	44965	1000	1000	16607	31	2064	29	30	37909	1000	37994	37994	37994	37994	38015
1004	37993	284	5	6	1998	1	0	37978	0	7267	50674	50680	87814	1003129	1	1000	49	34913	37993	37993	13140	5937	24394	87814	91431	182862	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44965	51	0	3878	44965	1000	1000	16617	28	2057	28	31	37909	1000	37994	37994	37994	37994	37994
1004	38232	285	7	7	1998	0	0	37978	0	7267	50674	50674	87814	1003114	0	1000	49	34913	37993	37993	13140	5937	24394	87814	91431	182864	37993	37996	1001	1	1001	1000	1000	44965	44965	0	44965	43	0	2004	44965	1000	1000	16607	30	2059	27	29	37909	1000	37994	37994	37994	37994	38008
1004	37993	284	5	6	1998	1	0	37978	0	7267	50674	50674	87814	1003129	0	1000	49	34913	37993	37993	13140	5937	24394	87814	91432	182864	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44965	53	0	2001	44965	1000	1000	16607	29	2063	29	31	37909	1000	37994	37994	37994	37994	38002
1004	37997	284	7	7	1998	0	0	37978	0	7267	50674	50674	87814	1003114	1	1000	49	34913	37993	37993	13140	5937	24394	87814	91431	182864	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44965	63	0	2190	44965	1000	1000	16607	29	2063	29	31	37909	1000	37994	37994	37994	37994	38007
1004	37993	284	6	7	1998	0	0	37978	0	7267	50697	50698	87814	1003114	1	1000	49	34913	37993	37993	13140	5937	24406	87814	91432	182864	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44965	0	0	2105	44965	1000	1000	16607	30	2063	28	31	37909	1000	37994	38029	37995	37994	37995
1004	37993	284	7	7	1998	0	0	37978	0	7267	50674	50674	87816	1003144	1	1000	49	34913	37993	37993	13140	5949	24402	87814	91432	182862	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44965	42	0	3896	44965	1000	1000	16607	31	2063	28	30	37909	1000	37994	37994	37994	37994	37994
1004	37998	285	7	7	1998	0	0	37978	0	7267	50674	50674	87814	1003114	1	1000	49	34913	37993	37993	13140	5943	24396	87814	91431	182862	37993	37993	1001	1	1001	1000	1000	44965	44965	0	44965	40	0	1998	44965	1000	1000	16605	30	2057	29	29	37909	1000	37994	37994	37994	37994	38005

Test 2: throughput

Code:

  stlxr w0, x1, [x6]
  add x6, x6, 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.9197

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20214	389171	2915	2	3	0	0	0	21452	7	2217	3	2312	113	128	389260	2152	3	69279	558538	298943	259588	788813	697502	12745658	11719193	0	10000	0	49	386827	389142	389147	83543	59212	181188	1486344	794488	778622	794485	1557264	389267	44	10001	1	20201	100	99	100	10000	10100	10000	100	232193	23	35626	1551	0	1892	230290	76	0	2544	104	20196	232130	10000	7	1664	1	0	0	209456	1	37	10978	56	64	389085	291442	10000	10100	389264	389264	389266	389230	389145
20204	389233	2915	4	0	0	0	0	21953	7	2355	1	2272	134	124	389245	2183	3	69280	558531	298939	259588	788810	697518	12747042	11718313	0	10000	14	49	386193	389267	389278	83478	59078	181302	1486321	794509	778616	794649	1557214	389264	44	10001	1	20201	100	99	100	10000	10100	10000	100	232192	39	34640	1565	0	1907	230299	72	0	2501	54	20256	232099	10000	7	1308	1	0	0	209454	1	56	10975	56	64	389204	291434	10000	10100	389150	389264	389267	389266	389262
20204	389268	2916	4	4	4	0	0	22005	7	2240	1	2288	117	124	389128	2114	4	69401	558538	298938	259600	788812	697506	12745403	11718297	0	10000	0	49	386195	389276	389264	83480	59079	181185	1486300	794520	778687	794505	1557344	389280	44	10001	1	20201	100	99	100	10000	10100	10000	100	232207	31	35099	1558	0	1899	230308	76	0	2518	54	20243	232167	10000	7	1712	1	0	0	209455	1	57	10972	56	64	389205	291556	10000	10100	389139	389139	389270	389143	389169
20204	389144	2916	4	0	0	0	0	21810	7	2239	1	2304	112	124	389134	1987	3	69402	558540	298957	259612	788816	697506	12746381	11717882	0	10000	0	49	386195	389268	389340	83549	59081	181323	1486319	794507	778684	794529	1557368	389141	44	10001	1	20201	100	99	100	10000	10100	10000	100	232184	31	41505	1582	0	1911	230311	76	4	2535	54	20710	232170	10000	7	1608	1	4	0	209454	1	58	10972	54	65	389217	291449	10000	10100	389283	389154	389262	389139	389142
20204	389147	2915	4	4	0	0	0	21898	359	2217	1	2344	125	124	389244	2148	4	69404	558530	298977	259594	788796	697498	12745412	11717391	0	10000	0	49	386063	389146	389418	83543	59206	181434	1486331	794665	778708	794521	1557726	389149	44	10001	1	20201	100	99	100	10000	10100	10000	100	232194	31	34971	1564	0	1894	230298	78	0	2514	80	20237	232139	10000	7	1348	1	0	0	209453	1	58	10972	56	66	389225	291444	10000	10100	389146	389146	389150	389146	389142
20204	389151	2914	4	0	4	0	0	21485	7	2215	1	2240	137	124	389250	2081	3	69404	558555	299069	259590	788793	697523	12746387	11718605	0	10000	0	49	386064	389268	389147	83483	59083	181195	1486318	794508	778612	794508	1557360	389276	44	10001	1	20201	100	99	100	10000	10100	10000	100	232210	31	35097	1584	0	1871	230295	78	8	2519	50	20268	232174	10000	7	1600	1	8	0	209458	1	56	10978	36	65	389084	291443	10000	10100	389293	389268	389145	389266	389451
20204	389139	2916	4	4	0	4	0	22057	7	2189	1	2336	122	124	389256	2149	3	69280	558544	298935	259592	788987	697495	12746306	11718284	0	10000	0	49	386080	389148	389145	83475	59206	181309	1486309	794521	778624	794488	1557358	389153	44	10001	1	20201	100	99	100	10000	10100	10000	100	232206	27	37833	1611	0	1887	230292	77	4	2524	54	22274	232158	10000	7	1740	1	0	0	209455	1	57	11086	55	66	389090	291437	10000	10100	389265	389417	389276	389266	389270
20204	389137	2917	4	0	0	0	4	21563	183	2226	1	2368	119	124	389251	2146	45	69404	558524	298953	259570	788789	697521	12745773	11719819	0	10000	14	49	386182	389266	389147	83555	59202	181311	1486309	794517	778620	794527	1557396	389269	44	10001	1	20201	100	99	100	10000	10100	10000	100	232190	31	37999	1599	0	1893	230314	74	8	2497	54	22179	232121	10000	7	1836	1	6	0	209454	1	57	10970	56	66	389204	291440	10000	10100	389267	389542	389146	389263	389264
20204	389141	2915	4	4	0	0	0	21693	7	2238	1	2264	117	124	389250	2128	47	69402	558530	298938	259588	788820	697513	12745324	11718790	0	10000	0	49	386207	389271	389150	83544	59079	181306	1486337	794522	778616	794507	1557224	389427	44	10001	1	20201	100	99	100	10000	10100	10000	100	232199	35	37108	1596	0	1881	230302	88	0	2484	50	20232	232221	10000	7	1560	1	0	0	209453	1	57	10978	56	64	389080	291432	10000	10100	389157	389140	389153	389448	389139
20204	389457	2915	4	0	4	0	0	21442	7	2234	1	2336	152	116	389250	2128	4	69279	558563	298949	259592	788991	697499	12745064	11719006	0	10000	0	49	386189	389148	389268	83538	59201	181194	1486331	794497	778638	794485	1557264	389149	44	10001	1	20201	100	99	100	10000	10100	10000	100	232171	31	36093	1615	0	1891	230300	87	4	2607	52	20236	232151	10000	7	1784	1	8	0	209468	1	57	10976	54	65	389204	291442	10000	10100	389267	389162	389399	389269	389142

1000 unrolls and 10 iterations

Result (median cycles for code): 38.9956

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20034	389968	2921	3	0	0	0	0	22014	7	2274	2	2088	68	244	389955	2122	3	70088	550230	290570	259670	760265	697579	12690320	11765299	1	10000	0	49	386869	0	389951	389976	70837	59900	188855	1457967	760832	759188	760840	1518384	389957	44	10001	1	20021	10	9	10	10000	10010	10000	10	232280	21	37825	1551	0	1919	230345	73	0	2534	108	20230	232259	10000	7	1760	1	0	0	201000	0	33	10978	31	34	389897	289806	10000	10010	389961	389963	389966	389950	389997
20024	389950	2921	3	4	0	1	3	21629	7	2266	2	1888	85	244	389936	2156	3	70088	550228	290557	259671	760272	697579	12690039	11765264	0	10000	0	49	386875	0	389952	389962	70829	59890	188873	1457964	760855	759193	760851	1518380	389962	265071	10001	1	20021	10	9	10	10000	10010	10000	10	232264	23	40108	1596	0	1906	230347	76	0	2538	112	20221	232307	10000	7	1568	1	0	0	200998	0	33	10974	31	33	389905	289804	10000	10010	389961	389949	389959	389962	389949
20024	389951	2921	3	0	0	0	0	22061	7	2277	2	1840	90	244	389935	2174	4	70088	550242	290553	259672	760284	697582	12690147	11765625	1	10000	0	98	386871	0	389961	389951	70827	59888	188867	1457848	760832	759192	760834	1518384	389947	44	10001	1	20021	10	9	10	10000	10010	10000	10	232282	19	37062	1599	0	1944	230358	75	1	2556	242	20243	232260	10000	7	1736	1	3	0	201000	0	33	10974	31	33	389905	289814	10000	10010	389962	389959	390024	389954	389960
20024	389946	2921	2	2	2	0	0	22271	7	2304	2	2152	77	248	389939	2187	4	70088	550232	290555	259667	760282	697579	12690169	11765938	1	10000	0	49	386873	0	389961	389956	70838	59895	188853	1457839	760830	759197	760842	1518402	389949	44	10001	1	20021	10	9	10	10000	10010	10000	10	232265	15	37681	1608	0	1917	230348	74	0	2564	280	20229	232260	10000	7	1520	1	0	0	200997	0	33	10974	37	39	389893	289809	10000	10010	389947	389949	389959	389949	389949
20024	389949	2921	3	0	0	0	0	21800	7	2282	2	2080	90	248	389946	2160	4	70088	550232	290558	259671	760268	697581	12689945	11765370	0	10000	0	49	386868	0	389967	389961	70826	59889	188852	1457852	760824	759173	760836	1518390	389946	44	10001	1	20021	10	9	10	10000	10010	10000	10	232292	23	33955	1574	0	1945	230347	75	3	2525	108	20261	232265	10000	7	1660	1	0	0	201001	0	33	10972	31	33	389888	289806	10000	10010	389964	389951	389965	389951	389953
20024	389960	2921	3	3	0	0	0	21531	7	2296	2	2024	71	252	389944	2093	4	70089	550222	290559	259668	760257	697590	12690060	11765369	1	10000	0	49	386870	0	389962	389951	70826	59890	188853	1457844	760828	759185	760848	1518418	389961	44	10001	1	20022	10	9	10	10000	10010	10000	10	232264	15	35979	1635	0	1906	230305	74	0	2510	256	20230	232264	10000	7	1540	1	0	0	200999	0	39	10978	31	32	389894	289807	10000	10010	389947	389964	389960	389951	389960
20024	389961	2921	2	2	0	0	0	21772	115	2258	2	2136	74	240	389946	2063	4	70099	550238	290556	259666	760270	697583	12689993	11765417	0	10000	0	49	386871	0	389961	389964	70824	59900	188864	1457848	760852	759272	760840	1518398	389952	44	10001	1	20021	10	9	10	10000	10010	10000	10	232278	23	36719	1581	0	1923	230347	69	0	2545	122	20204	232274	10000	7	1628	1	0	4	200999	0	39	10976	37	39	389903	289822	10000	10010	389964	389953	389963	389949	389951
20024	389963	2921	2	0	0	0	0	22008	7	2391	2	1872	82	244	389950	2142	4	70099	550224	290560	259668	760265	697574	12690776	11765202	0	10000	0	49	386869	0	389961	390001	70842	59908	188868	1457838	760855	759178	760834	1518378	389948	44	10001	1	20021	10	9	10	10000	10010	10000	10	232273	15	31581	1613	0	1892	230371	62	0	2538	108	20229	232252	10000	7	1668	1	0	0	200999	0	39	10977	31	33	389965	289810	10000	10010	389982	389963	389948	389957	389951
20024	389950	2920	3	3	0	0	0	22052	7	2233	2	2136	82	248	389946	2144	3	70099	550234	290557	259689	760270	697646	12690217	11765370	0	10000	0	49	386880	0	389962	389949	70828	59899	188871	1457830	760840	759193	760849	1518362	389958	44	10001	1	20021	10	9	10	10000	10010	10000	10	232273	23	35611	1580	0	1961	230326	59	0	2510	96	20233	232313	10000	7	1736	1	3	0	201000	0	40	10974	31	33	389886	289814	10000	10010	389951	389961	389951	389950	389959
20024	389963	2921	2	2	0	0	0	21939	7	2235	2	2136	72	248	389942	2130	3	70099	550224	290556	259669	760266	697577	12690087	11765317	0	10000	0	49	386870	0	389959	389951	70843	59900	188926	1457841	760840	759187	760852	1518406	389945	44	10001	1	20021	10	9	10	10000	10010	10000	10	232285	15	38256	1639	0	1905	230350	76	0	2504	194	20216	232269	10000	7	1688	1	0	0	200998	0	33	10974	31	33	389910	289808	10000	10010	389968	389954	389950	389949	389948

Test 3: throughput

Code:

  stlxr w0, x1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.0110

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10205	380101	2847	0	0	0	0	0	19998	0	0	0	31	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	0	380107	380107	130437	59953	248979	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	20013	458866	10000	0	10000	0	2	10	172682	1	131	11071	131	131	380168	1197	10000	100	380109	380108	380108	380108	380108
10204	380107	2847	0	0	0	0	0	19998	0	0	0	180	380092	0	70271	529276	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380107	130437	59963	248985	926433	19100	938443	19100	1876886	380109	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458868	10000	0	10000	0	0	10	172642	1	130	11059	131	131	380040	1197	10000	100	380108	380108	380108	380108	380108
10204	380107	2847	0	0	0	0	0	19998	0	0	0	181	380092	0	70272	529302	10697	518575	10697	915736	54384	10461909	0	10000	49	373975	0	380107	380107	130437	59943	248986	926433	19100	938443	19100	1876886	380107	380108	10001	1	10201	100	99	0	100	10000	100	10000	100	458872	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172640	1	130	11072	131	131	380040	1197	10000	100	380109	380108	380108	380110	380108
10204	380129	2848	0	0	0	0	0	19998	0	0	0	181	380092	0	70272	529272	10697	518579	10697	915736	54384	10461863	0	10000	49	377027	0	380124	380107	130437	59949	248989	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172640	1	130	11064	131	131	380040	1197	10000	100	380108	380110	380108	380108	380108
10204	380107	2847	0	0	0	0	0	20061	0	1	0	181	380092	0	70271	529272	10697	518619	10697	915736	54384	10461863	0	10000	49	377027	0	380107	380107	130456	59953	248985	926433	19100	938443	19100	1877128	380107	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172638	1	131	11068	131	131	380040	1197	10000	100	380108	380108	380108	380108	380108
10204	380107	2847	0	0	0	0	0	19998	0	0	0	181	380092	0	70271	529272	10697	518618	10697	915736	54384	10461863	0	10000	49	377027	0	380107	380107	130437	59947	248987	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172640	1	131	11070	131	131	380041	1197	10000	100	380108	380109	380108	380108	380108
10204	380107	2847	0	0	0	0	0	19998	0	0	0	181	380092	102	70398	529328	10697	518606	10697	915784	54395	10461863	0	10000	49	377029	0	380107	380107	130437	59960	248983	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458872	0	458866	0	458866	1	0	20941	458904	10000	0	10000	0	0	10	172640	1	131	11071	131	131	380040	1197	10000	100	380110	380108	380108	380108	380108
10204	380107	2847	0	0	0	0	0	19998	0	1	0	181	380092	0	70272	529272	10697	518581	10697	915736	71302	10462001	0	10000	49	377027	0	380107	380107	130473	59944	249001	926433	19100	938443	19100	1876886	380108	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	20052	458866	10000	0	10000	0	0	10	172640	1	131	11072	131	131	380040	1197	10000	100	380108	380108	380108	380108	380133
10204	380107	2847	0	0	0	0	0	19998	0	0	0	181	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	0	380107	380110	130437	59947	248979	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	20005	458866	10000	0	10000	0	0	10	172640	1	131	11072	130	130	380070	1197	10000	100	380125	380108	380108	380108	380108
10204	380109	2847	0	0	0	0	0	19998	0	0	0	181	380092	0	70271	529272	10697	518575	10697	915736	54390	10462461	0	10000	49	377027	0	380107	380107	130437	59963	248989	926433	19100	938443	19100	1876902	380107	380108	10001	1	10201	100	99	0	100	10000	100	10000	100	458866	0	458866	0	458866	4	0	19998	458866	10000	0	10000	0	0	10	172639	1	131	11071	131	131	380040	1197	10000	100	380108	380108	380108	380108	380108

1000 unrolls and 10 iterations

Result (median cycles for code): 38.0019

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10025	380019	2846	1	1	1	0	19998	14	0	380004	0	70267	519731	1067	518664	1067	915807	5424	10470786	1	10000	49	376941	0	380019	380019	138356	59949	249335	916874	1910	953892	1910	1908018	380019	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458971	16	458957	0	2	458971	0	1	20012	458958	10000	14	10000	1	0	0	169646	40	11078	40	40	379952	117	10000	10	380021	380020	380020	380022	380020
10024	380019	2846	1	1	0	0	19998	14	0	380004	0	70267	519730	1067	518664	1067	915807	5424	10470783	0	10000	49	376939	0	380021	380019	138355	59942	249345	916956	1910	953892	1910	1907784	380019	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458971	15	458958	0	0	458972	0	2	20012	458958	10000	14	10000	1	0	0	169646	42	11080	40	40	379952	117	10000	10	380020	380020	380021	380020	380020
10024	380019	2847	1	1	0	0	20106	14	0	380004	0	70267	519731	1067	518663	1067	915807	5424	10470783	0	10000	49	376939	0	380019	380019	138367	59942	249339	916874	1910	953894	1910	1907784	380019	380042	10001	1	10021	10	9	0	10	10000	10	10000	10	458974	14	458958	0	0	458971	0	0	20012	458957	10000	14	10000	1	2	0	169646	42	11080	41	42	379964	117	10000	10	380022	380020	380022	380020	380020
10024	380021	2846	1	1	1	1	19998	14	0	380004	2	70267	519730	1067	518667	1067	915807	5424	10470780	0	10000	98	376942	0	380019	380019	138355	59939	249351	916874	1910	953895	1910	1907790	380019	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458972	15	458956	0	1	458971	1	0	20012	458957	10000	14	10000	1	0	0	169646	41	11072	43	43	379961	117	10000	10	380020	380020	380020	380022	380020
10024	380019	2847	1	1	0	1	19998	14	0	380004	0	70267	519730	1067	518666	1067	915807	5424	10470780	0	10000	49	373903	3	380019	380021	138355	59939	249337	916874	1910	953892	1910	1907784	380019	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458971	15	458958	0	1	458972	0	1	20012	458957	10000	14	10000	1	1	0	169646	41	11079	40	41	379952	117	10000	10	380022	380020	380020	380020	380020
10024	380187	2854	1	2	2	2	19998	14	0	380004	0	70267	519731	1067	518664	1067	915911	5424	10471968	0	10000	49	376939	0	380019	380019	138355	59939	249335	916874	1910	953892	1910	1907784	380020	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458973	14	458958	0	1	458971	0	0	20012	458957	10000	14	10000	1	1	2	169647	40	11070	40	42	379952	117	10000	10	380021	380020	380020	380020	380020
10024	380019	2847	1	1	0	1	19998	14	0	380004	0	70267	519764	1067	518664	1067	915807	5424	10470786	0	10000	49	376939	0	380020	380019	138355	59939	249348	916874	1910	953892	1910	1907784	380019	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458973	14	458958	0	2	458972	0	1	20012	458958	10000	14	10000	1	1	0	169646	42	11080	41	44	379958	117	10000	10	380020	380020	380044	380020	380020
10024	380019	2847	1	0	1	1	19998	14	0	380004	0	70267	519731	1067	518599	1067	915807	5424	10470780	0	10000	49	376939	0	380019	380019	138355	59939	249335	916874	1910	953892	1910	1907784	380021	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458973	14	458957	0	1	458971	0	0	20012	458957	10000	14	10000	1	1	0	169646	42	11080	40	44	379958	117	10000	10	380043	380032	380020	380022	380020
10024	380019	2847	1	0	0	1	19998	14	0	380004	0	70267	519730	1067	518667	1067	915807	5424	10470785	0	10000	49	376939	0	380019	380019	138355	59943	249335	916874	1910	953892	1910	1907784	380019	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458974	14	458957	9	0	458972	0	2	20012	458958	10000	14	10000	1	2	0	169646	42	11079	42	42	379952	117	10000	10	380024	380020	380020	380020	380020
10025	380019	2847	1	1	0	1	19998	14	0	380004	0	70267	519730	1067	518666	1067	915806	5424	10470786	0	10000	49	376939	3	380028	380022	138355	59955	249348	916874	1910	953895	1910	1907784	380019	380019	10001	1	10021	10	9	0	10	10000	10	10000	10	458973	14	458958	0	0	458972	65	1	20052	458956	10000	14	10000	1	0	0	169646	42	11080	42	42	379961	117	10000	10	380020	380020	380020	380020	380020

STLXR (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations