Firestorm: ADCS (64-bit) measurements

Code:

  adcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1084	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	65	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	1	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	105	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	6	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  adcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8772	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	9	61	9920	25	10100	10126	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	15	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	12	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9918	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	192	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	183	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	153	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10116	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	3	9997	10000	10010	10036	10036	10036	10036	10036
10024	10083	75	0	1	21	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10131	10036	10036
10024	10035	75	0	1	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	103	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  adcs x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	18	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	6	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	84	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	31055	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647755	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	45	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	84	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	4	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	4	3	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	3	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	3	27	3	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	84	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	3	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	3	27	3	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	3	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	4	3	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	10	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	3	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	39	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	4	4	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 1->4

Chain cycles: 1

Code:

  adcs x0, x1, x2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	2	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	3	3	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20175
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	103	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	21	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	3	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	1	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20081	20243	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	536	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	22	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	0	49	16955	20035	20035	17428	3	17504	20020	20020	40252	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20066
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	6	61	19918	25	20020	20020	20020	1297297	0	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	9	61	19918	25	20020	20020	20020	1297297	0	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	15	61	19918	25	20020	20020	20020	1297297	0	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	0	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	285	19918	25	20020	20020	20020	1297297	0	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	1270	1	27	2	1	19995	20010	10010	20036	20036	20036	20036	20036

Test 5: Latency 4->2

Chain cycles: 1

Code:

  adcs x0, x1, x2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	21	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	40824	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	42	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20220	17425	7	17512	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20081	20036	20036	20036
20204	20035	150	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	536	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	72	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	2	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17439	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20082	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	156	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20081	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 6: Latency 4->3

Chain cycles: 1

Code:

  adcs x0, x1, x2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	82	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20082	20127	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	17137	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	12	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	2	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20066	150	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20022	10	9	10	20010	10010	0	0	1270	1	27	1	1	20050	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20092	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20079	150	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036

Test 7: Latency 4->4

Code:

  adcs x0, x1, x2

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	0	0	0	103	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	0	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	6	0	1	1	1	720	0	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	761	1	34	0	10082	10168	10100	10083	10134	10131	10130	10130
10204	10176	76	0	3	3	396	264	1	726	9926	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	1623	0	1	1	1	720	0	16	0	10013	10100	10100	10036	10036	10085	10129	10131
10204	10083	75	0	2	0	0	0	0	260	9927	70	10272	10247	10463	648334	0	49	6956	10174	10129	8696	15	8788	10381	10417	30565	10129	40	3	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	0	16	1	10013	10100	10100	10036	10036	10036	10086	10036
10204	10130	75	0	2	1	135	0	0	61	9926	70	10272	10224	10380	647712	0	49	7095	10083	10035	8695	21	8813	10210	10423	31121	10035	40	3	1	10201	100	99	10100	0	0	0	3	0	1	1	1	720	0	16	0	10013	10100	10100	10036	10036	10036	10083	10036
10204	10035	75	0	0	0	0	0	0	124	9927	68	10248	10224	10462	647712	0	49	6956	10178	10084	8693	21	8813	10298	10512	31151	10083	40	3	1	10201	100	99	10100	2	0	2	1628	2	1	1	1	720	0	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	7	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	0	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	88	0	61	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	3	0	1	1	1	720	0	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	81	0	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	0	16	0	10012	10100	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	0	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	1	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	0	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6956	0	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	0	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	2	0	0	640	3	27	3	4	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	0	10035	10035	8689	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	3	0	640	3	27	3	4	9997	10032	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	0	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	1	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	1	0	0	0	61	9918	25	10020	10020	10020	647296	1	49	6956	0	10035	10035	8678	10	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	0	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	54	3	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	0	10083	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	0	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	3	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  adcs x0, x8, x9
  ands xzr, xzr, xzr
  adcs x1, x8, x9
  ands xzr, xzr, xzr
  adcs x2, x8, x9
  ands xzr, xzr, xzr
  adcs x3, x8, x9
  ands xzr, xzr, xzr
  adcs x4, x8, x9
  ands xzr, xzr, xzr
  adcs x5, x8, x9
  ands xzr, xzr, xzr
  adcs x6, x8, x9
  ands xzr, xzr, xzr
  adcs x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53416	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	6378	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160172	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	11	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	18	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	702	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53391	400	0	0	0	0	416	25	160010	160010	160010	1029388	1	0	49	50294	53421	53374	33331	3	33351	160010	160020	240020	53374	52	2	1	160021	10	9	10	160010	10	0	0	0	0	0	10022	3	1	1	5	19	2	1	1	6	10	53370	160000	15	7	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	43	25	160010	160010	160082	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	3	0	10022	3	1	1	7	19	2	1	1	8	6	53370	160000	15	7	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	1	0	0	0	10022	3	1	1	4	19	2	1	1	7	7	53370	160000	15	7	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	1	0	15	0	10024	6	2	2	3	19	4	2	2	3	4	53370	160066	30	15	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	43	25	160010	160010	160010	1029388	0	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	10024	6	2	2	4	19	4	2	2	4	4	53370	160000	30	15	80010	53424	53375	53375	53375	53375
160024	53374	399	0	0	0	0	49	25	160010	160010	160010	1029388	0	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	10040	6	2	2	6	19	4	2	2	6	6	53370	160000	30	15	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	842	25	160010	160076	160010	1029388	0	1	49	50294	53374	53374	33331	3	33351	160010	160020	240128	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	10024	6	2	2	4	19	4	2	2	7	6	53370	160000	30	15	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	43	25	160010	160010	160010	1029388	0	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	12	0	10024	6	2	2	3	19	4	2	2	4	3	53370	160000	30	15	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	12	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	10022	3	1	1	7	19	2	1	1	7	4	53370	160000	15	7	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	175	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	10022	3	1	1	7	19	2	1	1	7	6	53370	160000	15	7	80010	53375	53375	53375	53375	53375

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  adcs x0, x4, x5
  adcs x1, x4, x5
  adcs x2, x4, x5
  adcs x3, x4, x5

Initialization

  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13418	106	0	0	0	0	15	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	0	0	13383	13412	13412	6026	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40215	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	108	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	0	0	13383	13412	13412	6026	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	153	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	0	0	13383	13412	13412	5553	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	0	447	0	25	50100	40100	10000	40100	10000	574746	80000	0	0	13383	13412	13412	5553	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	0	0	13383	13412	13412	5553	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	0	0	13383	13412	13412	6026	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	0	0	13383	13412	13412	5538	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	6	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	0	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	0	0	13383	13412	13412	5553	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	0	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13407	100	2	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	104	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	101	0	0	131	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	68	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	3140	2	19	2	2	13379	40000	40010	13383	13383	13383	13383	13383

ADCS (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 4->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 9: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations