Firestorm: MUL (32-bit) measurements

Code:

  mul w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	22	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	1	16	1	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	1	16	1	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	3	73	1	16	1	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	1	0	73	1	16	1	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	6	73	1	16	1	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	3	73	1	16	2	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	2	0	73	1	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	82	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	3	73	1	16	2	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	2809	25	1000	1000	1025	162099	0	40	3033	3033	2676	3	2891	1000	1000	2000	3077	296	1	1	1001	1000	0	0	73	1	16	1	1	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	1	16	2	1	2863	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  mul w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	61	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30208	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	128	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	8	28741	10100	10200	20200	30033	290	2	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	536	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	536	29809	25	10100	10100	10100	1665186	1	6	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	6	1	16	1	1	29863	10000	10100	30034	30164	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	0	0	105	29809	25	10010	10010	10010	1664736	0	49	26953	30076	30033	28548	7	28789	10010	10020	20020	30033	296	2	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	103	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	1	640	2	16	2	2	29864	10000	10010	30076	30034	30034	30034	30034
10024	30033	224	1	264	0	61	29809	47	10010	10010	10090	1664736	0	49	26953	30206	30033	28560	3	28763	10134	10169	20020	30033	296	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	2	640	4	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  mul w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	103	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	1	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	346	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	2	2	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	251	29809	25	10100	10100	10100	1665186	0	49	26953	30070	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30207	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	3	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	48	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	1	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034

Test 4: throughput

Count: 8

Code:

  mul w0, w8, w9
  mul w1, w8, w9
  mul w2, w8, w9
  mul w3, w8, w9
  mul w4, w8, w9
  mul w5, w8, w9
  mul w6, w8, w9
  mul w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40053	300	0	0	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	414	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	1	5110	1	16	1	1	40032	80000	80100	40081	40036	40036	40036	40036
80204	40035	300	0	0	0	39	25	80125	80125	80100	400500	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	5	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	299	0	0	0	40	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	1	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	61	25	80100	80100	80100	400626	0	49	36955	40035	40035	29970	0	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40042	299	0	0	489	40	25	80010	80010	80010	400050	0	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	3	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	552	40	25	80010	80010	80010	400050	0	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	447	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	299	0	0	234	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	21	40	25	80010	80010	80010	400050	0	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	2	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	486	40	25	80010	80010	80010	400050	0	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	2	2	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	42	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	540	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	57	40	25	80010	80010	80010	400050	0	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	1	1	40032	80044	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	40	25	80010	80010	80010	400050	0	49	36955	40035	40035	29992	0	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	1	16	1	1	40032	80000	80010	40036	40036	40036	40036	40036

MUL (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations