Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MUL (32-bit)

Test 1: uops

Code:

  mul w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10043033220061280925100010001000161686140303330332676328911000100020003033296111001100000731161128631000100030343034303430343034
10043033220061280925100010001000161686040303330332676328911000100020003033296111001100000731161128631000100030343034303430343034
10043033220061280925100010001000161686140303330332676328911000100020003033296111001100003731161128631000100030343034303430343034
10043033230061280925100010001000161686140303330332676328911000100020003033296111001100010731161128631000100030343034303430343034
10043033230061280925100010001000161686040303330332676328911000100020003033296111001100006731161128631000100030343034303430343034
10043033230061280925100010001000161686140303330332676328911000100020003033296111001100003731162128631000100030343034303430343034
10043033230061280925100010001000161686140303330332676328911000100020003033296111001100020731162228631000100030343034303430343034
10043033230082280925100010001000161686040303330332676328911000100020003033296111001100003731162128631000100030343034303430343034
10043033220061280925100010001025162099040303330332676328911000100020003077296111001100000731161128631000100030343034303430343034
10043033230061280925100010001000161686140303330332676328911000100020003033296111001100000731162128631000100030343034303430343034

Test 2: Latency 1->2

Code:

  mul w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)0318193f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102043003322500612980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343003430034
102043003322500612980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343003430034
102043003322400612980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343003430034
102043003322500612980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343003430034
102043003322500612980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343020830034
102043003322500612980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343003430034
1020430033225001282980925101001010010100166518616492695330033300332852682874110100102002020030033290211020110099100101001000007106116112986310000101003003430034300343003430034
1020430033225005362980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343003430034
102043003322500612980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430034300343003430034
1020430033225005362980925101001010010100166518616492695330033300332852632874110100102002020030033290111020110099100101001000007106116112986310000101003003430164300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03191e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100243003322500010529809251001010010100101664736049269533007630033285487287891001010020200203003329621100211091010010100640216222986410000100103003430034300343003430034
10024300332250006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100640216222986410000100103003430034300343003430034
10024300332250006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100640216222986410000100103003430034300343003430034
100243003322500010329809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010101640216222986410000100103007630034300343003430034
1002430033224126406129809471001010010100901664736049269533020630033285603287631013410169200203003329611100211091010010100640216222986410000100103003430034300343003430034
10024300332250006129809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010102640416222986410000100103003430034300343003430034
10024300332250006129809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100640216222986410000100103003430034300343003430034
10024300332250006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100640216222986410000100103003430034300343003430034
10024300332250006129809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100640216222986410000100103003430034300343003430034
10024300332250006129809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100640216222986410000100103003430034300343003430034

Test 3: Latency 1->3

Code:

  mul w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020430033225010329809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100010710116112986310000101003003430034300343003430034
1020430033225034629809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100220710116112986310000101003003430034300343003430034
102043003322506129809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343003430034
1020430033225025129809251010010100101001665186049269533007030033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343003430034
102043003322506129809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343003430034
102043003322506129809251010010100101001665186149269533003330033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343020730034
102043003322506129809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343003430034
102043003322506129809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343003430034
102043003322506129809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343003430034
102043003322506129809251010010100101001665186049269533003330033285263287411010010200202003003329011102011009910010100100000710116112986310000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)0318191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250000612980925100101001010010166473614926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473604926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473604926953300333003328548328763100101002020020300332961110021109101001010300640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473614926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473604926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
100243003322500480612980925100101001010010166473604926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473614926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473614926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473614926953300333003328548328763100101002020020300332961110021109101001010000640216222986410000100103003430034300343003430034
10024300332250000612980925100101001010010166473604926953300333003328548328763100101002020020300332961110021109101001010001640216222986410000100103003430034300343003430034

Test 4: throughput

Count: 8

Code:

  mul w0, w8, w9
  mul w1, w8, w9
  mul w2, w8, w9
  mul w3, w8, w9
  mul w4, w8, w9
  mul w5, w8, w9
  mul w6, w8, w9
  mul w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204400533000004025801008010080100400500049369554003540035299700329993801008020016020040035901180201100991008010010000005110216114003280000801004003640036400364003640036
80204400353000004025801008010080100400500049369554003540035299700329993801008020016020040035901180201100991008010010000005110116114003280000801004003640036400364003640036
802044003530000041425801008010080100400500149369554003540035299700329993801008020016020040035901180201100991008010010000015110116114003280000801004008140036400364003640036
80204400353000003925801258012580100400500049369554003540035299700329993801008020016020040035901180201100991008010010000005110516114003280000801004003640036400364003640036
80204400353000004025801008010080100400500049369554003540035299700329993801008020016020040035901180201100991008010010000005110116114003280000801004003640036400364003640036
80204400352990004025801008010080100400500149369554003540035299700329993801008020016020040035901180201100991008010010000005110116114003280000801004003640036400364003640036
80204400353000004025801008010080100400500049369554003540035299700329993801008020016020040035901180201100991008010010000005110116114003280000801004003640036400364003640036
80204400353000004025801008010080100400500049369554003540035299700329993801008020016020040035901180201100991008010010000005110116114003280000801004003640036400364003640036
80204400353000004025801008010080100400500049369554003540035299700329993801008020016020040035901180201100991008010010000015110116114003280000801004003640036400364003640036
80204400353000006125801008010080100400626049369554003540035299700329993801008020016020040035901180201100991008010010000005110116114003280000801004003640036400364003640036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800244004229900489402580010800108001040005004936955400354003529992033001580010800201600204003590118002110910800101000050200316114003280000800104003640036400364003640036
800244003530000552402580010800108001040005004936955400354003529992033001580010800201600204003590118002110910800101000050200116114003280000800104003640036400364003640036
800244003530000447402580010800108001040005014936955400354003529992033001580010800201600204003590118002110910800101000050200116114003280000800104003640036400364003640036
800244003529900234402580010800108001040005014936955400354003529992033001580010800201600204003590118002110910800101000050200116114003280000800104003640036400364003640036
80024400353000021402580010800108001040005004936955400354003529992033001580010800201600204003590118002110910800101000050200216114003280000800104003640036400364003640036
800244003530000486402580010800108001040005004936955400354003529992033001580010800201600204003590118002110910800101000050200116224003280000800104003640036400364003640036
80024400353000042402580010800108001040005014936955400354003529992033001580010800201600204003590118002110910800101000050200116114003280000800104003640036400364003640036
800244003530000540402580010800108001040005014936955400354003529992033001580010800201600204003590118002110910800101000050200116114003280000800104003640036400364003640036
80024400353000057402580010800108001040005004936955400354003529992033001580010800201600204003590118002110910800101000050200116114003280044800104003640036400364003640036
8002440035300000402580010800108001040005004936955400354003529992033001580010800201600204003590118002110910800101000050200116114003280000800104003640036400364003640036