Firestorm: PACDZB measurements

Code:

  pacdzb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	30	0	187	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	153	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	1	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	1	6	0	61	5824	25	1003	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	4	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	77	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6635	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7070	7030
1004	7068	70	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	2	0	0	73	1	93	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	15	0	89	5824	25	1003	1000	1000	178330	0	49	3949	7029	7029	6634	3	6818	1000	1000	1000	7069	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	86	2	85	1	2	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	68	0	21	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7068	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6817	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	6	0	103	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  pacdzb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	676	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	689	0	0	0	0	0	12	0	345	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	4	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	0	12	0	726	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	1	0	0	0	0	0	710	1	79	1	1	69796	10100	2	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	0	0	0	103	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	678	0	0	0	0	0	9	0	117	59824	25	10200	10200	10200	1808330	0	49	66949	3	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	1	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	678	0	0	0	0	0	3	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	0	0	0	726	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70056	70030	70030	70030
10204	70029	678	0	0	0	0	0	24	0	104	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	677	0	0	0	0	0	12	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	675	0	0	0	0	0	986	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	3	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	679	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	690	0	0	0	0	0	61	59824	25	10020	10020	10020	1807376	0	98	66949	3	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	3	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	679	0	0	0	0	0	726	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	679	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	692	0	0	0	0	0	89	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	679	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	691	0	0	0	0	0	103	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	689	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	680	0	0	0	0	0	250	59824	25	10020	10020	10020	1807430	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  pacdzb x0
  pacdzb x1
  pacdzb x2
  pacdzb x3
  pacdzb x4
  pacdzb x5
  pacdzb x6
  pacdzb x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80204	80063	698	0	0	0	1	0	0	88	35	47	80200	80200	80200	401000	0	49	77000	80035	80035	69983	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	3	0	0	0	0	5110	2	25	2	3	80058	80121	0	80100	80036	80036	80036	80036	80036
80204	80081	700	0	0	0	0	2	0	88	35	46	80200	80200	80200	401000	0	49	77001	80035	80035	69966	3	70017	80200	80234	80200	80081	164	1	1	80201	100	99	80100	2	0	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	750	0	0	0	0	0	12	0	718	46	80200	80221	80266	401000	0	49	76955	80035	80035	69985	3	69984	80222	80200	80233	80035	164	1	1	80201	100	99	80100	0	2	0	1	0	0	0	0	0	0	0	5136	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80082	80036
80204	80035	750	0	0	0	0	0	132	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69984	8	69984	80200	80200	80200	80080	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	0	5110	2	33	2	2	80058	80100	0	80100	80036	80036	80081	80036	80036
80204	80035	700	0	0	0	0	0	0	0	78	25	80220	80200	80200	401000	0	49	76955	80035	80035	69966	7	69984	80200	80200	80232	80035	164	2	1	80201	100	99	80100	0	2	2	0	0	0	0	0	0	0	0	5110	2	25	2	2	80091	80100	0	80100	80036	80036	80082	80081	80036
80204	80035	700	1	0	0	0	0	0	0	35	25	80200	80200	80244	401107	0	49	76955	80035	80080	69985	3	69984	80200	80234	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	0	5110	2	33	2	2	80025	80121	0	80100	80036	80036	80036	80036	80081
80204	80035	700	1	0	1	1	0	132	0	700	25	80200	80200	80200	401107	0	49	76955	80035	80035	69985	3	69984	80200	80200	80232	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	2	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80081	80036	80036	80036
80204	80035	749	1	1	0	1	0	0	88	79	25	80200	80200	80244	401000	0	49	76955	80035	80081	70003	3	69984	80200	80235	80200	80081	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80127
80204	80035	748	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	77001	80081	80081	69966	16	69984	80200	80200	80200	80080	164	2	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	0	5122	2	33	2	2	80057	80100	0	80100	80036	80036	80082	80036	80036
80204	80081	699	1	0	0	1	0	0	0	226	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80222	80200	80200	80035	164	1	1	80201	100	99	80100	2	0	0	0	0	0	0	0	0	0	0	5110	2	33	2	2	80058	80100	0	80100	80036	80036	80036	80082	80081

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	696	0	0	0	0	1	12	0	189	25	80020	80020	80020	400100	0	49	77000	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	17	25	10	9	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	165	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	8	25	9	10	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80081	699	0	0	0	1	0	0	0	728	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	5020	8	25	9	9	80024	80030	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	63	25	80020	80020	80042	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	5020	10	25	9	10	80024	80010	0	80010	80036	80082	80036	80036	80036
80024	80035	749	0	0	0	0	0	0	0	763	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	2	0	0	0	0	3	5020	10	25	8	8	80024	80010	20	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	12	0	6034	25	80020	80020	80020	400100	0	49	76955	80035	80080	69988	3	70006	80020	80054	80020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	3	5020	8	25	9	8	80059	80010	0	80010	80036	80036	80067	80036	80036
80024	80035	749	0	0	0	0	0	12	0	77	47	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	8	25	11	9	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	290	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	2	0	5020	10	25	11	9	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	12	0	77	25	80020	80041	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	5020	9	25	9	9	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	695	0	0	0	0	0	132	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	1	0	0	490	5020	8	25	9	9	80024	80010	0	80010	80036	80036	80036	80036	80036

PACDZB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations