Firestorm: AUTDA measurements

Code:

  autda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	71	1	1	15	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	5	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	66	1	1	0	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	66	1	1	0	2	110	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	65	1	1	0	2	68	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	66	1	1	0	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	7	6818	1000	1000	2086	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	66	1	1	0	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	65	1	1	0	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	65	1	1	0	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	66	1	1	0	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	66	1	1	0	2	68	5824	25	1000	1000	1000	178330	0	49	3949	7029	7109	6623	3	6818	1000	1000	2082	7029	870	1	1	1001	1000	0	0	76	4	85	4	4	6789	1000	0	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3a	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch call indir mispred nonspec (ca)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	619	0	0	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70069	70030	70030	70069
10204	70029	621	0	1	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10103	10100	70030	70030	70030	70030	70069
10204	70029	651	1	0	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	1	98	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	2	0	1	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	0	497	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	1	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70054	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	619	0	0	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	1	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	0	61	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	0	103	59824	0	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	617	0	0	0	0	21	0	1410	59824	25	10023	10023	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70059	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	657	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68583	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	3	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	629	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	94	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	0	640	2	79	3	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	126	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	124	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	1	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	0	232	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	3	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  autda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5e	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	699	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	1	0	0	0	0	0	1910	2	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	745	0	0	0	0	0	0	0	0	103	69799	25	20200	20200	20200	4942601	0	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	41	0	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	706	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	2	1	30201	100	99	30100	0	0	6	0	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	702	0	0	0	2	1	0	88	0	103	69799	25	20200	20200	20200	4942601	0	0	49	76989	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	63	0	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	702	0	0	0	0	0	12	0	0	103	69799	25	20200	20200	20200	4942601	0	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	4	2	0	3	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80056	80030	80030	80030	80030
30204	80029	701	0	0	0	0	0	0	0	1	749	69799	25	20200	20200	20200	4942601	0	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	5	0	0	0	0	0	1910	1	72	1	1	79794	20122	0	30100	80030	80030	80030	80030	80030
30204	80029	744	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	702	0	0	0	0	0	0	0	0	89	69799	25	20200	20200	20200	4942601	0	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	702	0	0	0	0	0	12	0	0	156	69799	25	20200	20200	20200	4942601	0	1	49	75717	80029	80074	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30205	80029	702	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	1	0	6	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch indir mispred nonspec (c6)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
30024	80029	696	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76209	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	1	0	9	0	1890	3	72	4	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	700	0	0	0	0	0	0	0	12	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	76044	3	76208	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	3	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	700	0	0	0	0	0	1	1	12	0	1055	69799	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	2	0	0	0	1890	3	72	3	3	79803	20010	349	30010	80030	80030	80030	80030	80030
30024	80067	700	0	0	0	0	0	0	0	0	0	89	69799	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76211	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	1	0	9	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	700	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	716	0	0	0	0	0	0	0	12	0	61	69799	25	20020	20020	20020	4960612	1	49	76949	0	80029	80775	75983	16	76309	20020	20517	41310	80029	144	1	1	30021	10	9	30010	0	0	1	0	0	0	1890	3	72	3	3	80055	20015	0	30010	80030	80030	80030	80344	80030
30024	80159	701	0	0	0	0	0	0	0	9	0	150	69799	25	20052	20020	20086	4952048	1	49	76949	0	80029	80029	75983	3	76211	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	700	0	0	0	0	0	0	2	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	2	1	30021	10	9	30010	0	0	0	0	3	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	696	0	0	0	0	0	0	0	12	0	103	69799	44	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	1	1890	3	72	3	3	79808	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	699	0	0	0	0	0	0	0	12	0	1203	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	3	0	1890	3	72	4	4	79823	20010	0	30010	80030	80030	80030	80030	80030

Test 4: throughput

Count: 8

Code:

  autda x0, x8
  autda x1, x8
  autda x2, x8
  autda x3, x8
  autda x4, x8
  autda x5, x8
  autda x6, x8
  autda x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	46	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80204	80041	698	0	0	0	0	12	0	77	0	0	25	80200	80200	80200	401000	0	49	76955	80168	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	2	0	0	5110	3	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	698	0	0	0	0	0	0	35	0	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	3	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	645	0	0	0	0	12	0	35	0	0	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	745	0	0	0	0	0	0	35	0	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	744	0	0	0	0	0	0	63	0	0	25	80200	80200	80200	401000	0	98	76966	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	2	0	0	0	0	5110	3	25	2	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	0	35	0	0	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	697	0	0	0	0	0	0	320	0	0	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	5110	3	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	9	0	35	0	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	701	0	0	0	0	0	0	45	0	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	2	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	12	0	77	0	0	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	3	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	643	0	0	0	0	0	0	0	0	0	77	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	3	0	0	0	5020	2	25	0	0	4	3	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	698	0	0	0	0	0	0	0	0	0	77	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5033	4	25	0	3	0	4	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	703	0	0	0	0	0	0	0	0	0	700	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5020	3	25	0	5	0	4	6	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	58	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5020	2	25	0	3	0	4	6	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	225	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70037	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	3	0	5020	4	25	10	0	0	2	4	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	0	12	0	35	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5020	4	33	6	0	0	4	2	80024	80052	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	756	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	3	0	0	0	5020	4	25	6	0	0	7	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	704	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	0	0	5020	4	25	0	0	0	4	4	80024	80010	80010	80490	80447	80580	80712	80626
80024	81092	698	0	0	1	1	1	14	18	1608	1056	4328	346	80335	80377	80350	401598	0	49	77640	0	80670	80762	70258	69	70533	80353	80522	160290	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5020	4	25	0	0	0	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	703	0	0	0	0	0	0	0	0	0	510	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	0	0	5020	4	25	0	0	0	4	2	80024	80010	80010	80036	80036	80036	80036	80036

AUTDA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations