Firestorm: LDRSH (register, sxtw, 32-bit) measurements

Code:

  ldrsh w0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	0	0	0	0	0	45	1	0	3	388	3	7	7	19	25	1000	1000	1000	14159	394	394	216	3	255	1000	1000	2000	394	77	1	1	1001	0	1000	1000	0	1000	0	43	1039	0	0	39	1039	6	1	39	43	0	0	73	2	16	2	2	395	10	10	4	1000	395	399	399	399	399
1004	394	3	0	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	394	398	221	3	256	1000	1000	2000	398	77	1	1	1001	0	1000	1000	1	1000	0	43	1038	0	0	39	1039	6	1	39	44	0	0	73	2	16	2	2	400	13	13	5	1000	404	404	404	404	404
1004	403	3	1	1	0	0	0	66	0	0	3	388	3	7	7	19	25	1000	1000	1000	15555	404	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1021	19	43	1059	1	1	60	1040	6	1	59	43	19	0	73	2	16	2	2	400	13	13	5	1000	404	404	403	405	403
1004	403	3	1	0	1	0	0	65	0	0	3	388	3	7	7	20	25	1000	1000	1000	15501	406	403	225	3	260	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	44	1059	1	0	60	1039	6	1	60	43	19	2	73	2	16	2	2	400	13	13	5	1000	404	404	407	404	404
1004	403	3	1	0	0	0	0	67	0	0	2	387	3	7	7	20	25	1000	1000	1000	15480	402	403	225	3	261	1000	1000	2000	405	85	1	1	1001	0	1000	1000	0	1020	19	43	1059	1	1	60	1040	6	1	58	43	19	1	73	2	16	2	2	400	13	13	5	1000	404	403	403	404	404
1004	406	3	1	0	1	0	0	66	0	0	2	388	2	7	7	18	25	1000	1000	1000	15523	403	403	225	3	262	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	20	43	1058	1	1	61	1040	6	1	59	43	19	1	73	2	16	2	2	400	13	13	5	1000	404	404	404	404	404
1004	403	3	1	1	0	0	0	67	1	0	2	388	3	7	7	20	25	1000	1000	1000	15555	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	1	60	1040	6	1	58	43	19	1	73	2	16	2	2	400	13	13	5	1000	404	404	404	403	404
1004	403	3	1	1	1	0	0	66	0	0	3	388	3	7	7	19	25	1000	1000	1000	15526	404	402	225	3	261	1000	1000	2000	402	85	1	1	1001	0	1000	1000	0	1020	21	43	1059	1	2	61	1039	6	1	59	43	19	1	73	2	16	2	2	400	13	13	5	1000	404	403	403	404	404
1004	403	2	1	0	0	0	0	69	0	0	2	388	3	7	7	20	25	1000	1000	1000	15506	403	403	225	3	262	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	45	1059	1	2	60	1039	6	1	59	43	19	0	73	2	16	2	2	400	13	14	5	1000	404	404	405	404	404
1004	403	3	1	0	0	0	0	66	0	0	3	388	3	7	7	19	25	1000	1000	1000	15555	403	406	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1021	19	43	1059	1	0	60	1040	6	1	59	43	19	1	73	2	16	2	2	400	13	13	5	1000	404	404	404	404	404

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	1	1	0	0	0	70020	69747	59706	25	40104	30103	10001	30100	10000	616175	3342062	1	49	66967	70047	70047	64631	0	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	1	2610	1	71	1	1	69813	30003	6	6	0	10000	30100	70067	70049	70053	70052	70048
40204	70050	524	1	1	1	0	0	70058	69781	59709	25	40100	30100	10001	30100	10000	616005	3341470	0	49	66970	70035	70035	64643	0	3	64938	40100	30200	10000	60596	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	1	0	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70053	70054	70051	70051	70051
40204	70047	524	0	0	1	0	0	70032	69735	59695	25	40104	30103	10001	30100	10000	616175	3342206	0	49	66955	70047	70050	64631	0	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	0	0	1	2610	1	71	1	1	69813	30003	9	6	9	10000	30100	70331	70143	70058	70085	70039
40204	70050	524	0	0	0	1	0	70035	69735	59709	25	40104	30103	10001	30100	10000	616005	3341470	0	49	66970	70047	70050	64631	0	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	1	2610	1	71	1	1	69810	30003	9	0	0	10000	30100	70051	70051	70048	70048	70048
40204	70047	525	0	0	6	1	0	70032	69764	59706	25	40100	30103	10001	30100	10000	616005	3342062	1	49	66967	70047	70047	64643	0	3	64953	40314	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	1	2610	1	71	1	1	69810	30003	6	6	9	10000	30100	70052	70054	70051	70051	70051
40204	70050	525	0	0	1	0	0	70032	69764	59709	25	40100	30103	10000	30100	10000	616005	3342206	0	49	66970	70047	70050	64646	0	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	1	0	10000	0	0	0	2610	1	71	1	1	69813	30003	6	6	0	10000	30100	70053	70039	70051	70051	70036
40204	70047	525	0	0	0	1	0	70020	69735	59695	25	40100	30103	10001	30100	10000	616015	3342062	1	49	66967	70047	70035	64689	0	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	2610	1	71	1	1	69813	30000	9	6	6	10000	30100	70050	70050	70036	70048	70048
40204	70035	525	0	0	0	0	0	70035	69781	59695	25	40104	30103	10000	30100	10000	616005	3342206	1	49	66970	70047	70051	64646	0	3	64963	40100	30398	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	1	2610	1	71	1	1	69810	30000	6	6	9	10000	30100	70415	70052	70065	70038	70048
40204	70047	524	0	0	0	0	0	70032	69764	59695	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66970	70050	70050	64631	0	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	1	0	0	2610	1	71	1	1	69810	30003	9	6	9	10000	30100	70054	70048	70051	70048	70036
40204	70047	524	0	0	0	0	0	70032	69764	59744	25	40100	30100	10001	30100	10000	616005	3342062	0	49	66972	70047	70047	64643	0	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	1	0	1	2610	1	71	1	1	69813	30003	9	0	0	10000	30100	70048	70049	70036	70048	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	524	0	1	0	70060	69775	59710	25	40010	30013	10000	30010	10000	617018	3342398	0	1	49	66955	70054	70054	64672	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	2520	3	71	0	2	2	69798	30003	0	10	10	10000	30010	70055	70036	70055	70036	70036
40024	70054	525	0	1	0	70041	69779	59695	25	40014	30013	10000	30010	10102	617077	3342542	0	1	49	66955	70054	70035	64653	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	2	0	0	2520	2	71	0	2	2	69798	30003	0	10	0	10000	30010	70036	70036	70052	70036	70055
40024	70054	524	0	6	1	70020	69778	59695	25	40014	30013	10000	30010	10000	617068	3342254	0	1	49	66955	70051	70054	64672	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	0	2520	2	71	0	2	2	69798	30003	13	10	13	10000	30010	70055	70055	70056	70052	70055
40024	70035	525	0	1	1	70020	69778	59715	25	40014	30013	10000	30010	10000	617068	3341470	0	1	49	66971	70054	70054	64653	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	0	0	0	0	2520	2	71	0	2	2	69814	30003	13	0	0	10000	30010	70036	70055	70052	70055	70036
40024	70051	543	0	1	0	70039	69743	59695	25	40014	30013	10004	30010	10000	617018	3342398	0	1	49	66974	70054	70150	64672	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	2520	2	71	0	2	2	69817	30003	13	13	13	10000	30010	70036	70055	70055	70055	70052
40024	70054	525	0	1	1	70039	69743	59713	25	40010	30013	10001	30010	10000	616991	3342254	0	1	49	66974	70035	70054	64672	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	3	71	0	2	2	69814	30000	13	13	13	10000	30010	70036	70055	70036	70036	70036
40024	70054	524	0	1	1	70039	69778	59695	25	40014	30013	10000	30010	10000	617068	3342254	0	1	49	66974	70035	70035	64653	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	2520	2	71	0	2	2	69814	30003	0	13	13	10000	30010	70052	70052	70052	70055	70052
40024	70035	524	0	0	0	70020	69778	59713	25	40010	30013	10001	30010	10000	617018	3342398	0	1	49	66974	70054	70051	64653	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	0	2520	2	71	0	2	2	69817	30000	0	0	13	10000	30010	70055	70055	70055	70052	70055
40024	70051	525	0	0	1	70020	69743	59695	42	40014	30013	10001	30010	10000	617576	3342302	0	0	49	66971	70054	70035	64653	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	0	1	0	0	0	2520	2	71	0	2	2	69814	30000	10	10	13	10000	30010	70055	70036	70055	70036	70036
40024	70054	525	0	1	1	70020	69775	59713	25	40014	30013	10001	30010	10000	617090	3342398	0	1	49	66974	70054	70035	64672	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	3	71	0	2	2	69817	30003	13	13	13	10000	30010	70055	70036	70055	70055	70055

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70145	524	1	0	0	0	0	1	0	1	0	70036	69789	59714	25	40104	30103	10002	30100	10000	616014	3342254	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2611	2	71	3	3	69814	30003	10	10	10	10000	30100	70055	70054	70053	70052	70052
40204	70051	525	0	0	0	0	0	1	0	1	0	70036	69782	59710	25	40100	30103	10000	30100	10000	616014	3342254	49	66971	0	70035	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2611	3	71	3	3	69814	30003	10	10	0	10000	30100	70056	70054	70036	70036	70052
40204	70051	524	0	0	0	0	0	4	0	1	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70052	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	1	10000	0	0	0	10000	1	1	2611	2	71	3	2	69814	30003	10	10	10	10000	30100	70055	70054	70052	70036	70052
40204	70051	524	0	0	0	0	0	1	0	1	0	70020	69782	59710	25	40104	30103	10000	30100	10000	616014	3342254	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2611	3	71	3	3	69814	30003	10	10	10	10000	30100	70412	70058	70052	70077	70052
40204	70051	525	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40100	30103	10001	30100	10000	616014	3342254	49	66971	0	70051	70051	64650	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2611	3	71	3	2	69814	30000	10	10	10	10000	30100	70059	70090	70052	70052	70052
40204	70051	524	0	0	0	0	0	13	0	1	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3341470	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	3	10000	0	1	2611	2	71	2	3	69814	30000	10	10	0	10000	30100	70039	70053	70052	70052	70052
40204	70051	524	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40104	30100	10001	30100	10000	616014	3342254	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	1	0	0	10000	1	1	2611	3	71	3	3	69814	30003	10	10	0	10000	30100	70086	70083	70056	70052	70052
40204	70051	524	0	0	0	0	0	7	0	0	0	70036	69786	59710	25	40104	30103	10000	30100	10000	616014	3341470	49	66971	0	70051	70051	64647	3	65013	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2611	3	71	3	2	69814	30000	10	0	0	10000	30100	70054	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	0	10000	1	1	2611	3	71	3	3	69814	30003	10	10	0	10000	30100	70412	70053	70052	70084	70036
40204	70051	524	0	0	1	1	0	1	0	1	0	70036	69782	59710	25	40104	30103	10000	30100	10000	616014	3342254	49	66971	0	70051	70051	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2611	2	71	3	2	69814	30003	10	0	0	10000	30100	70054	70053	70055	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70054	524	0	0	0	0	0	0	1	1	0	70040	69775	59710	25	40010	30013	10002	30010	10000	616991	3342254	49	66971	70051	70035	64731	3	64966	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	0	0	0	2520	9	71	4	8	69823	30006	10	0	10	10000	30010	70052	70052	70060	70052	70036
40024	70095	524	0	0	0	0	0	0	1	1	0	70039	69778	59713	25	40014	30013	10000	30010	10000	616991	3341470	49	66955	70054	70035	64653	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	3	71	3	6	69823	30003	13	0	13	10000	30010	70061	70042	70042	70047	70061
40024	70041	524	1	1	0	1	0	0	2	0	0	70020	69778	59713	25	40014	30013	10001	30010	10000	616991	3342254	49	66974	70054	70054	64672	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	0	1	0	2520	5	71	4	9	69823	30006	13	13	13	10000	30010	70042	70058	70061	70058	70042
40024	70060	525	1	1	0	1	0	0	1	1	0	70039	69743	59713	25	40010	30013	10000	30010	10000	617018	3341470	49	66974	70054	70035	64653	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	4	71	4	9	69804	30006	10	0	13	10000	30010	70058	70061	70061	70061	70061
40024	70060	525	1	1	0	0	0	0	2	0	0	70020	69743	59695	25	40014	30013	10001	30010	10000	617018	3342398	49	66971	70054	70054	64672	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10001	0	0	10000	1	0	1	0	2520	8	71	8	3	69804	30003	0	13	10	10000	30010	70061	70058	70042	70061	70042
40024	70060	524	1	1	0	0	0	0	2	0	0	70039	69778	59695	25	40014	30013	10000	30010	10000	617018	3342398	49	66955	70054	70035	64669	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	7	71	7	3	69826	30003	13	13	13	10000	30010	70061	70061	70061	70061	70061
40024	70060	525	1	1	0	1	0	0	2	0	0	70039	69781	59713	25	40014	30013	10001	30154	10000	617018	3342398	49	66977	70042	70051	64655	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	0	0	1	0	2554	8	71	8	8	69823	30003	13	13	13	10000	30010	70058	70061	70058	70042	70061
40024	70041	525	1	0	0	0	0	0	2	0	0	70039	69743	59713	25	40014	30013	10001	30010	10000	617068	3342398	49	66974	70054	70054	64669	3	64960	40010	30020	10000	60020	20000	70117	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	0	1	1	0	2520	8	71	8	8	69896	30006	10	10	0	10000	30010	70058	70061	70061	70042	70058
40024	70060	525	1	1	0	0	0	0	2	1	0	70039	69778	59713	25	40014	30013	10000	30010	10000	617018	3342398	49	66974	70054	70054	64672	3	64960	40010	30020	10065	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	0	0	0	2520	8	71	4	7	69804	30003	13	13	13	10000	30010	70042	70042	70042	70042	70061
40024	70060	524	1	0	0	0	0	1	2	1	0	70082	69778	59695	25	40014	30013	10001	30010	10000	617018	3342398	49	66955	70054	70035	64672	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	7	71	4	4	69823	30003	0	10	13	10000	30010	70058	70042	70061	70061	70061

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	0	0	45	0	0	0	1	26712	2	12	12	17	25	80100	100	80000	100	80015	500	1167303	1	49	23647	26727	26707	16635	6	16679	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	126	80000	14	39	80039	6	0	35	43	1	1	1	5118	2	16	1	1	26704	6	0	4	80000	100	26775	26730	26712	26734	26723
80204	26727	200	0	1	1	0	0	1	0	1	26712	0	0	18	18	25	80100	100	80000	100	80016	500	1167875	1	49	23647	26722	26727	16650	6	16659	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	0	80039	0	35	80000	6	1	35	39	1	1	1	5118	1	16	1	1	26704	0	6	2	80000	100	26779	26739	26874	26728	26728
80204	26722	200	0	0	0	41	0	1	0	1	26696	2	12	12	16	25	80100	100	80000	100	80015	500	1166596	1	49	23647	26707	26707	16635	6	16674	80114	200	80024	200	160048	26722	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80035	1	39	80039	6	0	35	39	1	1	1	5118	1	16	1	1	26719	10	6	2	80000	100	26790	26733	26791	26725	26728
80204	26727	200	1	0	0	41	0	1	0	2	26707	0	12	0	17	25	80100	100	80000	100	80016	500	1166596	0	49	23627	26707	26707	16650	6	16678	80115	200	80024	200	161210	26731	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80035	2	35	80039	6	1	0	0	1	1	1	5118	1	16	1	1	26724	10	6	4	80000	100	26781	26729	26755	26731	26723
80204	26727	200	0	0	0	45	0	0	0	1	26707	0	0	0	12	25	80100	100	80000	100	80015	500	1177116	0	49	23627	26722	26722	16650	6	16679	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80000	0	39	80035	6	1	35	39	1	1	1	5118	1	16	1	1	26704	10	0	4	80000	100	26771	26738	26736	26728	26708
80204	26715	200	0	0	0	0	0	1	0	1	26707	2	12	12	12	25	80100	100	80000	100	80015	500	1167875	1	49	23814	26722	26707	16650	6	16679	80115	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	0	80039	0	1	39	43	1	1	1	5118	1	16	1	1	26704	6	6	0	80000	100	26775	26732	26825	26708	26708
80204	26707	200	0	0	0	41	0	1	0	1	26692	2	0	0	13	25	80100	100	80000	100	80014	500	1167875	0	49	23627	26727	26727	16650	6	16659	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	39	80039	6	1	35	0	1	1	1	5118	1	16	1	1	26724	10	6	4	80000	100	26785	26717	26792	26708	26708
80204	26725	200	0	0	1	45	0	1	0	1	26707	0	12	0	14	25	80100	100	80000	100	80014	500	1167875	0	49	23642	26722	26722	16635	6	16659	80114	200	80024	200	160048	26722	72	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	0	80039	0	0	80000	6	1	0	39	1	1	1	5118	1	16	1	1	26719	10	10	2	80000	100	26734	26708	26723	26723	26723
80204	26722	201	0	0	0	45	0	0	0	0	26712	2	18	0	18	25	80100	100	80000	100	80015	500	1177116	0	49	23647	26722	26722	16650	6	16674	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	0	80035	0	1	35	39	1	1	1	5118	1	16	1	1	26719	6	0	0	80000	100	26764	26729	26744	26736	26723
80204	26707	200	0	0	1	45	0	0	0	2	26731	2	12	0	15	25	80100	100	80000	100	80014	500	1165856	0	49	23642	26731	26731	16639	6	16807	80114	200	80024	200	160048	26722	72	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	0	80039	0	39	80039	6	1	0	39	1	1	1	5118	1	16	1	1	26719	10	0	4	80000	100	26780	26730	26720	26729	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	1	0	44	1	0	1	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	49	23647	26728	26731	16672	3	16688	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	0	80039	0	39	80039	6	1	39	43	5020	2	16	1	2	26841	0	10	4	80000	10	26709	26729	26729	26728	26728
80024	26708	200	1	1	45	1	0	1	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1167201	49	23647	26708	26727	16672	3	16708	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	0	80039	0	38	80039	6	1	39	44	5020	1	16	2	2	26845	10	10	4	80000	10	26732	26729	26729	26732	26732
80024	26731	200	0	0	53	1	0	1	26712	2	1	1	16	25	80010	10	80000	10	80000	50	1166750	49	23648	26731	26708	16672	3	16707	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	0	80039	0	38	80039	6	0	0	43	5020	1	16	1	3	26710	0	10	0	80000	10	26729	26709	26728	26728	26709
80024	26727	200	1	0	45	0	0	1	26713	2	12	1	19	25	80010	10	80000	10	80000	50	1168843	49	23647	26727	26728	16672	3	16707	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	0	80000	0	38	80040	6	0	0	0	5020	1	16	1	1	26724	10	14	7	80000	10	26729	26728	26728	26709	26728
80024	26727	200	0	0	45	0	0	1	26713	0	12	12	19	25	80010	10	80000	10	80000	50	1166886	49	23647	26731	26708	16672	3	16707	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	0	80039	0	38	80000	6	1	39	44	5020	1	16	1	1	26739	0	0	4	80000	10	26728	26728	26728	26729	26729
80024	26728	200	0	0	0	1	0	1	26693	2	0	0	16	25	80010	10	80000	10	80000	50	1166750	49	23648	26708	26728	16672	3	16707	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	0	80039	0	39	80000	6	1	0	0	5020	2	16	2	2	26832	10	10	4	80000	10	26709	26728	26728	26728	26729
80024	26728	200	0	0	45	1	0	1	26716	2	12	1	16	25	80010	10	80000	10	80000	50	1168843	49	23648	26727	26708	16672	3	16708	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	0	80038	0	0	80000	6	0	39	44	5020	1	16	2	2	26724	10	10	0	80000	10	26728	26728	26728	26732	26729
80025	26768	200	0	0	87	0	0	0	26712	0	1	12	19	25	80010	10	80000	10	80000	50	1168843	49	23647	26728	26728	16672	3	16688	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	44	0	80038	0	39	80038	6	0	39	43	5020	1	16	1	1	26825	10	0	4	80000	10	26729	26729	26732	26728	26728
80024	26731	200	0	0	0	0	0	1	26715	2	1	1	16	25	80010	10	80000	10	80000	50	1168843	49	23628	26727	26728	16676	3	16708	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	41	80000	0	1	39	44	5020	1	16	1	1	26724	10	14	4	80000	10	26732	26732	26709	26732	26896
80024	26731	200	0	0	45	0	0	1	26716	0	0	12	16	25	80010	10	80000	10	80000	50	1167501	49	23648	26727	26727	16652	3	16707	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80000	0	0	80000	6	1	39	44	5020	1	16	1	1	26862	14	10	4	80000	10	26728	26732	26728	26732	26709

LDRSH (register, sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations