Firestorm: SETF8 measurements

Code:

  setf8 w1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	1035	8	0	598	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	0	1080	1035	816	3	882	1000	1000	2000	1035	104	1	1	1001	1000	1	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	79	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	103	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	5	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036

Test 2: Latency 2->1

Chain cycles: 1

Code:

  setf8 w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	0	45	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	339	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	15	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20215	20035	17425	6	17487	20112	20319	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	0	3173	3	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	123	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	12	0	82	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	24	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	399	0	61	19930	25	20100	20100	20112	1297233	49	16955	20080	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	0	1	1	1	1318	16	0	0	20011	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	39	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	429	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	2	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	33	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	12	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	3	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	82	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	21	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	1	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	6	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 2->2

Code:

  setf8 w0

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	1	536	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	1	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	1	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	82	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	1	82	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	1	82	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	76	0	0	1	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	6	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	1	166	9927	25	10200	10200	10210	647712	1	49	6956	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	33	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036
10204	10035	76	0	12	0	103	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	7	8736	10210	10224	20248	10035	110	1	1	10201	100	99	10100	0	0	0	1	1	1	719	16	10010	10100	100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	3	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	6	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	3	27	4	3	10025	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	156	61	9918	25	10020	10020	10020	647296	49	7000	10035	10035	8686	7	8779	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	2	840	640	3	27	3	3	10025	10010	10	10036	10036	10036	10036	10036
10024	10035	75	1	198	103	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	12	82	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	4	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	915	9918	25	10020	10020	10020	647296	49	6956	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	66	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	104	1	1	10021	10	9	10010	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
160204	53408	400	1	0	1	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	0	0	0	176	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160063	1	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	4	0	30	0	0	28	27	160120	160120	160128	1061989	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	0	0	27	0	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	0	0	0	0	0	49	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	399	1	0	1	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409
160204	53408	400	1	0	1	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	49	50328	53408	53408	33347	6	33357	160128	160240	160240	53408	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	1	1	1	10119	1	16	1	1	53405	160020	0	100	53409	53409	53409	53409	53409

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53379	400	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10022	3	1	1	5	19	2	1	1	4	3	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	27	0	0	10022	3	1	1	4	19	2	1	1	3	4	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	6	0	0	10022	3	1	1	4	19	2	1	1	4	4	53370	160000	15	7	10	53375	53375	53375	53375	53411
160024	53374	400	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	3	0	0	10022	3	1	1	4	19	2	1	1	4	3	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	410	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	76	6	0	0	10022	3	1	1	4	19	2	1	1	4	3	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	3	0	0	10022	3	1	1	4	19	2	1	1	4	3	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	47272	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	3	0	0	10022	3	1	1	4	19	2	1	1	3	4	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	6	0	0	10022	3	1	1	4	19	2	1	1	4	3	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	21	0	1	10022	3	1	1	4	19	2	1	1	4	3	53370	160000	15	7	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	81	12	0	0	10022	3	1	1	4	19	2	1	1	3	4	53370	160000	15	7	10	53375	53375	53375	53375	53375

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  setf8 w0
  setf8 w0
  setf8 w0
  setf8 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3354

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13456	110	0	0	0	0	0	0	0	28	0	25	50122	40112	10010	40143	10013	575127	80097	0	13395	13416	13416	6137	2467	7	7110	50156	40251	10013	80302	20026	13416	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	3	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13417	13417	13417	13417
50204	13416	100	0	0	0	0	0	0	0	28	0	25	50122	40112	10084	40143	10013	575127	80097	0	13395	13416	13416	6137	2456	7	7110	50156	40251	10013	80302	20026	13416	13415	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13417	13417	13417	13417
50204	13416	100	0	0	0	0	0	0	0	51	0	25	50122	40112	10010	40143	10013	575127	80097	0	13395	13416	13416	6139	2467	7	7110	50156	40251	10013	80302	20026	13415	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	30	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13417	13417	13417	13417
50204	13416	100	0	0	0	0	0	0	0	28	0	25	50122	40112	10010	40143	10013	575127	80097	1	13395	13415	13416	6139	2456	7	7110	50156	40251	10013	80302	20026	13415	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13417	13417	13417	13417
50204	13416	101	0	0	0	0	0	0	0	28	0	25	50122	40112	10010	40143	10013	575127	80097	0	13395	13416	13416	6139	2456	7	7110	50156	40251	10013	80302	20026	13416	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13417	13417	13417	13417
50204	13416	100	0	0	0	0	12	0	0	28	0	25	50122	40112	10010	40143	10013	575127	80097	0	13395	13416	13416	6139	2467	7	7110	50156	40251	10013	80302	20026	13415	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	0	1	1	1	3221	0	1	16	0	0	13413	40012	100	13417	13417	13417	13417	13417
50204	13416	100	0	0	0	0	12	0	0	28	0	25	50122	40112	10010	40143	10013	575127	80680	0	13395	13416	13416	6139	2467	7	7110	50156	40251	10013	80302	20026	13416	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	1	0	0	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13417	13417	13417	13416
50204	13416	100	0	0	0	0	0	0	0	28	0	25	50122	40112	10010	40143	10013	575127	80097	0	13395	13416	13416	6137	2467	7	7110	50156	40251	10013	80302	20026	13415	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	1	0	0	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13416	13417	13417	13417
50204	13416	100	0	0	0	0	0	0	0	28	0	24	50122	40112	10010	40143	10013	575127	80097	0	13395	13416	13416	6137	2467	7	7110	50156	40251	10013	80302	20026	13416	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	3	0	1	1	1	3221	0	0	16	0	0	13413	40012	100	13417	13417	13416	13417	13417
50204	13416	100	0	0	0	0	0	0	0	28	0	25	50122	40112	10010	40143	10013	575127	80097	0	13395	13416	13416	6137	2467	7	7110	50156	40251	10013	80302	20026	13416	13416	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	9	0	1	1	1	3220	0	0	16	0	0	13413	40012	100	13417	13417	13417	13417	13417

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13384	101	1	0	0	0	0	45	25	50010	40010	10000	40010	10000	570031	80000	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3141	0	0	21	19	19	16	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3141	0	0	19	19	18	19	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	6	0	3141	0	0	18	19	17	20	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	101	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3	0	3141	0	0	19	19	19	19	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3141	0	0	15	19	16	9	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	1	0	0	3141	0	0	20	19	16	19	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	121	25	50010	40010	10000	40010	10000	573456	80191	13353	13382	13382	5575	3784	3	7134	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3	0	3141	0	0	19	19	11	19	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	101	0	0	0	0	36	45	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3141	0	0	19	19	19	16	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	399	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3141	0	0	19	19	19	19	13379	40000	10	13429	13383	13383	13383	13383
50024	13382	101	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3141	0	0	19	19	19	19	13379	40000	10	13383	13383	13383	13383	13383

SETF8

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations