Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADR

Test 1: uops

Code:

  adr x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03193f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004535303525100010001000500015355353703388100010005359011100110000731211152910001000536536536536536
1004535403525100010001000500015355353703388100010005359011100110000731211152910001000536536536536536
1004535403525100010001000500015355353703388100010005359011100110000731211152910001000536536536536536
1004535405825100010001000500015355353703388100010005359011100110000731211152910001000536536536536536
1004535403525100010001000500015355353703388100010005359011100110000731211152910001000536536536536536
1004535403525100010001000500005355353703388100010005359011100110000731211152910001000536536536536536
1004535404525100010001000500005355353703388100010005359011100110000731211152910001000536536536536536
1004535403525100010001000500005355353703388100010005359011100110000731211152910001000536536536536536
1004535403525100010001000500015355353703388100010005359011100110000731211152910001000536536536536536
1004535403525100010001000500015355353703388100010005359011100110000731211152910001000536536536536536

Test 2: throughput

Count: 8

Code:

  adr x0, .+4
  adr x1, .+4
  adr x2, .+4
  adr x3, .+4
  adr x4, .+4
  adr x5, .+4
  adr x6, .+4
  adr x7, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802044011430000000109258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000009035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000305110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086
80204400853000000035258010080100801004005004937005400854008530020330038801008020020040085901180201100991008010010000005110221224007980000801004008640086400864008640086

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800244005629900352580010800108001040005014936960400874004029998330016800108002020400409011800211091080010100000050200000320534003580000800104004140041400414004140041
800244004030000352580010800108001040005014936960400404004029998330016800108002020400409011800211091080010100000050200000520534003580000800104004140041400414004140041
800244004030000352580010800108001040005004936960400404004029998330016800108002020400409011800211091080010100000050200000520554003580000800104004140041400414004140041
800244004030000352580010800108001040005004936960400404004029998330016800108002020400409011800211091080010100000050200000520554003580000800104004140041400414004140041
800244004030000352580010800108001040005004936960400404004029998330016800108002020400409011800211091080010100000050200000520354003580000800104004140041400414004140041
800244004030000352580010800108001040005014936960400404004029998330016800108002020400409011800211091080010100000050200000520354003580000800104004140041400414004140041
800244004030000352580010800108001040005004936960400404004029998330016800108002020400409011800211091080010100000050200000420534003580000800104004140041400414004140041
800244004030000352580010800108001040005014936960400404004029998330016800108002020400409011800211091080010100000050200000520534003580000800104004140041400414004140041
80024400403000035258001080010800104000501493696040040400402999833001680010800202040040901180021109108001010020505450480001420634007180000800104004140041400414004140041
800244004030000352580010800108001040005014936960400404004029998330016800108002020400409011800211091080010100000050200050520534003580000800104004140041400414004140041