Firestorm: ADR measurements

Code:

  adr x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	535	3	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	58	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	45	25	1000	1000	1000	5000	0	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	0	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	535	90	1	1	1001	1000	0	73	1	21	1	1	529	1000	1000	536	536	536	536	536

Count: 8

Code:

  adr x0, .+4
  adr x1, .+4
  adr x2, .+4
  adr x3, .+4
  adr x4, .+4
  adr x5, .+4
  adr x6, .+4
  adr x7, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40114	300	0	0	0	0	0	109	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	9	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	3	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086
80204	40085	300	0	0	0	0	0	35	25	80100	80100	80100	400500	49	37005	40085	40085	30020	3	30038	80100	80200	200	40085	90	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	21	2	2	40079	80000	80100	40086	40086	40086	40086	40086

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40056	299	0	0	35	25	80010	80010	80010	400050	1	49	36960	40087	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	3	20	5	3	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	5	20	5	3	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	5	20	5	5	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	5	20	5	5	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	5	20	3	5	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	5	20	3	5	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	4	20	5	3	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	0	0	5	20	5	3	40035	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	2	0	505	4	5048	0	0	0	1	4	20	6	3	40071	80000	80010	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	29998	3	30016	80010	80020	20	40040	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	0	5	0	5	20	5	3	40035	80000	80010	40041	40041	40041	40041	40041

ADR

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations