Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (immediate, 32-bit)

Test 1: uops

Code:

  cmn w0, #3
  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
10043692036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043693036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043692036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043693036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043692036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043692036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043693036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043692036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043692036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370
10043693036251000100010005000136936920632251000100010003696611100110000073118113661000370370370370370

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmn w0, #3
  cset x0, cc
  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020420035150024611993025201002010020112129723314916955200352003517425617487201122022420224200351041120201100991002010010100001111318116212001120000101002003620036200362003620036
202042003515000611993025201002010020112129723314916955200352003517425617487201122022420320200351041120201100991002010010100001111318116112001120000101002003620036200362003620036
202042003515000611993025201002010020112129723314916955200352003517425617487201122022420224200351041120201100991002010010100001111318116112001120000101002003620036200362003620036
202042003515000611993025201002010020112129723304916955200352003517425617487201122022420224200351041120201100991002010010100001111318116112001120000101002003620036200362003620036
202042003515000611993025201002010020112129723304916955200352003517425617487201122022420224200351041120201100991002010010100001111318116112001120000101002003620036200362003620036
202042003515000611993025201002010020112129723304916955200352003517425617487201122022420224200351041120201100991002010010100001111318116112001120000101002003620036200362003620036
202042003515000611993025201002010020112129723314916955200352003517425617487201122022420224200351041120201100991002010010100201111318116112001120000101002003620067200362003620036
202042003515000611993025201002010020112129723314916955200352003517425617487201122022420224200351041120201100991002010010100001111318116122001120000101002003620036200362003620036
2020420035150021611993025201002010020112129723304916955200352003517425617487201122022420224200351041120201100991002010010100001111318116112001120000101002003620036200362003620036
202042003515000611993025201002010020112129723304916955200352003517425617487201122022420224200351041120201100991002010010100001111318116112001120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002420035150001051991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010001270227111999520000100102003620036200362003620036
2002420035150001031991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010011270127111999520000100102003620036200362003620036
200242003515000611991825200102001020010129724714916955200352003517458317504200102002020020200351041120021109102001010010001270127111999520000100102003620036200362003620036
2002420035150005361991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010001270127111999520000100102003620036200362003620036
200242003515000821991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010001270127111999520000100102003620036200362003620036
2002420035150007221991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010001270127111999520000100102003620036200362003620036
200242003515000611991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010001270127111999520000100102003620036200362003620036
200242003515000611991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010011270127111999520000100102003620036200362003620036
2002420035150007261991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010001270127121999520000100102003620036200362003620036
200242003515000611991825200102001020010129724714916955200352003517428317504200102002020020200351041120021109102001010010001270127111999520000100102003620036200362003620036

Test 3: throughput

Count: 8

Code:

  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3344

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267632001001000008533801158011580121400590049236702675126751166761016686801218023080230267516611802011009910080100100000000022251283253326747800151002675126751267522675226751
8020426750200100100000643480115801158012140059014923670267502675016676916686801218023080230267516611802011009910080100100000000022251283253326748800151002675126751267512675126751
8020426751201100100090643380115801158012140059004923671267502675016676916686801218023080230267516611802011009910080100100000000022251283253326748800151002675126751267512684326751
8020426750200100100000873380115801158012140059004923671267502675016676916686801218023080230267506611802011009910080100100000000022251283253326748800151002675126751267512675126751
8020426751200100100000643480115801158012140059004923670267502675116676916686801218023080230267506611802011009910080100100000000022251293253326747800151002675126752267522675226751
80204267502011001000006433801158011580121400590049236712675026750166761016686801218023080230267516611802011009910080100100000300012251283253326748800151002675126751267512675126751
8020426750201100100000643380115801158012140059014923670267512675016676916686801218023080230267516611802011009910080100100000000022251283253326748800151002675226752267512675126751
80204267502001000000006434801158011580121400590049236702675126750166761016686801218023080230267506611802011009910080100100000000022251293253326748800151002675126751267512675226751
8020426751200100100000184734801158011580121400590149236702675026750166761016686801218023080230267516611802011009910080100100000000022251283253326748800151002675126751267512675126751
8020426750201100100000643380115801158012140059004923671267502675116676916686801218023080230267516611802011009910080100100000000022251283253326747800151002675226751267512675226752

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03mmu table walk data (08)09191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242671020000000142258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050207182572670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050208185682670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050205185672670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050205185782670180000102670626706267062670626752
80024267051990000035258001080010800104000500492362526743267051666531668380010800208002026705661180021109108001010000050208185682670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050207183692670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050205184582670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050205185892670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050205184782670180000102670626706267062670626706
80024267052000000035258001080010800104000500492362526705267051666531668380010800208002026705661180021109108001010000050207185782670180000102670626706267062670626706