Firestorm: SBCS (32-bit) measurements

Code:

  sbcs w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	300	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	3	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	15	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	291	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  sbcs w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	76	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	75	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	71	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	8	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	1	6	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	2023	9920	25	10100	10100	10100	647152	1	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	47	9	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	0	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	27	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	12	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	45	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	6	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	66	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	124	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	3	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	51	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	103	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  sbcs w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	76	9	103	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	18	0	710	1	27	2	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	21	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	1	0	737	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	5	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	84	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	51	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	5	27	4	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	5	27	5	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	5	27	5	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	210	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	5	27	4	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	30	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	4	640	4	27	4	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	124	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	5	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	5	27	5	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	124	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	5	27	5	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	4	27	5	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	45	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	640	5	27	5	4	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 1->4

Chain cycles: 1

Code:

  sbcs w0, w1, w2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	18	0	0	61	19926	25	20200	20200	20200	1297650	1	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	30	0	0	61	19926	25	20200	20200	20200	1297650	0	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	82	19926	25	20200	20200	20200	1297650	0	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	251	19926	25	20200	20200	20200	1297650	1	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	1310	0	0	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20025	20035	158	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	2	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	189	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	149	0	0	45	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	3	61	19918	25	20020	20020	20102	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	2	36	0	0	0	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	156	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	1	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	147	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	935	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	0	0	0	2	1	19995	20010	10010	20036	20036	20036	20036	20036

Test 5: Latency 4->2

Chain cycles: 1

Code:

  sbcs w0, w1, w2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	1	1	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	135	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	61	19930	25	20124	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	4540	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	2	0	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	111	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	61	19930	25	20122	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	1	0	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	82	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	127	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	1	0	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	1	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	654	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	3	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	82	19917	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 6: Latency 4->3

Chain cycles: 1

Code:

  sbcs w0, w1, w2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1320	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	156	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	114	0	1	1	1	1320	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	45	20146	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1	1	1	1320	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	15	0	108	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	7	0	0	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	81	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	3	0	1630	0	1	1	1	1319	0	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	9	108	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	6	0	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	2	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	45	20010	20032	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	103	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	0	0	0	6	0	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	1	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	4	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 7: Latency 4->4

Code:

  sbcs w0, w1, w2

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	1	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	24	0	61	9927	25	10200	10200	10210	647712	1	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10012	10100	10100	10036	10036	10036	10086	10036
10204	10035	75	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	1	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10012	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	18	0	61	9927	25	10200	10200	10210	647712	1	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	12	0	61	9927	25	10200	10200	10210	647712	1	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10012	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	1	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9927	25	10200	10200	10210	648361	1	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	719	0	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	3	0	536	9927	25	10200	10200	10210	647712	1	0	49	6955	10035	10035	8673	7	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10012	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	51	0	61	9927	25	10200	10200	10210	647712	1	0	49	6955	10035	10035	8673	7	8736	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9927	25	10200	10200	10210	647712	1	0	49	6955	10035	10035	8673	7	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	1	1	720	0	16	10013	10100	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	3	9997	10010	10010	10084	10036	10036	10036	10036
10024	10035	75	0	120	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	21	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	294	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	291	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	4	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	103	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	1	6	61	9918	72	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	6	9997	10010	10010	10036	10036	10036	10083	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	33	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	1	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  sbcs w0, w8, w9
  ands xzr, xzr, xzr
  sbcs w1, w8, w9
  ands xzr, xzr, xzr
  sbcs w2, w8, w9
  ands xzr, xzr, xzr
  sbcs w3, w8, w9
  ands xzr, xzr, xzr
  sbcs w4, w8, w9
  ands xzr, xzr, xzr
  sbcs w5, w8, w9
  ands xzr, xzr, xzr
  sbcs w6, w8, w9
  ands xzr, xzr, xzr
  sbcs w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53432	400	0	0	0	169	25	160100	160100	160100	1063588	1	49	50324	0	53404	53452	33339	3	33359	160100	160200	240200	53453	52	1	1	160201	100	99	100	160100	100	0	1	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	276	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	1	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	12	1830	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	2027	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	15	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	1890	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240311	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	1759	25	160100	160100	160215	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	9	1142	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	1930	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	142	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160273	240200	53404	52	1	1	160201	100	99	100	160100	100	4	1	1755	10110	1	19	3	2	53715	160140	80100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53380	400	0	0	0	0	0	0	0	0	0	0	0	49	25	160010	160010	160010	1029388	1	1	0	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	49	0	0	0	0	10023	8	4	1	1	39	19	1	1	1	16	26	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	1	0	0	0	0	0	0	0	92	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	26	0	0	0	0	10023	8	5	1	1	22	19	1	1	1	28	25	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	1	0	0	0	0	0	0	0	92	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	40	0	0	0	0	10023	8	5	1	1	26	19	1	1	1	21	25	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	1	0	0	0	0	0	0	0	92	25	160010	160010	160010	1029388	1	1	0	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	4	2	471	0	0	10023	8	5	1	1	26	19	1	1	1	26	26	53370	160068	16	8	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	1	0	0	0	0	0	0	0	92	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	54	0	3	0	0	10023	8	5	1	1	27	19	1	1	1	25	26	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	399	1	0	0	1	0	0	0	0	0	0	0	92	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	26	0	0	0	0	10023	8	5	1	1	18	19	1	1	1	24	20	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	399	1	0	0	1	0	0	0	0	0	0	0	92	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	23	0	0	0	0	10023	8	5	1	1	25	19	1	1	1	26	26	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	1	0	0	0	0	0	0	0	115	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	52	0	0	0	0	10023	8	5	1	1	16	19	1	1	1	26	16	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	1	0	0	0	0	0	0	0	472	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	4	2	3	0	0	10023	8	5	1	1	21	19	1	1	1	28	20	53370	160000	16	8	80010	53375	53375	53375	53375	53375
160024	53374	399	1	0	0	1	0	0	0	0	0	0	0	92	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	35	0	0	0	0	10023	8	5	1	1	27	19	1	1	1	27	26	53370	160000	16	8	80010	53375	53375	53375	53375	53375

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  sbcs w0, w4, w5
  sbcs w1, w4, w5
  sbcs w2, w4, w5
  sbcs w3, w4, w5

Initialization

  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13455	100	0	0	0	0	0	45	0	13396	25	50100	40100	10000	40100	10000	587442	80000	1	13383	13412	13412	6026	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	3	0	45	0	0	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	0	0	45	0	0	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	6026	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	1	0	0	45	0	0	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	45	0	0	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	5538	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	45	0	0	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	0	0	45	0	0	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	5553	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	0	0	45	0	0	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	5929	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	45	0	0	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	0	45	0	0	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	5553	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13404	100	12	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	15	19	0	8	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	106	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7140	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	8	19	0	8	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	8	19	0	8	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	21	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	8	19	0	8	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	3	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	7	19	0	7	7	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	6	19	0	8	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	101	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5951	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	2	1	50021	10	9	10	40010	10000	10	0	0	3140	8	19	0	8	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5951	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	7	19	0	7	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	8	19	0	7	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	3	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	3140	8	19	0	9	8	13379	40000	40010	13383	13383	13383	13383	13383

SBCS (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 4->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 9: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations