Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CINC (64-bit)

Test 1: uops

Code:

  cinc x0, x0, hi
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103576191725100010001000622501103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103576191725100010001000622500103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103576191725100010001000622500103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103586191725100010001000622500103510358053882100010003000103510411100110001000073127119901000100010361036103610361082
1004103586191725100010001000622501103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103586191725100010001000622501103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103576191725100010001000622500103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103586191725100010001000622501103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103576191725100010001000622501103510358053882100010003000103510411100110001000073127119901000100010361036103610361036
1004103586191725100010001000622500103510358053882100010003000103510411100110001000073127119901000100010361036103610361036

Test 2: Latency 1->2

Code:

  cinc x0, x0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575009619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610036
1020410035750002519920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610172
102041003575000619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010040071012711999210000101001003610036100361003610036
102041003575000619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610036
102041003575000619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610036
102041003575000619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610036
102041003575010619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610036
102051003575010619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610036
102041003575000619920251010010100101006471521496955100351003586563873210100102003020010035102111020110099100101001010000071012711999210000101001003610036100361003610036
102041003575000619920251010010100101006471520496955100351003586563873210100102003020010035102111020110099100101001010010071012711999210000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750004419918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010000064022722999310000100101003610036100361003610036
100241003575000619918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010201064022722999310000100101003610036100361003610036
100241003575000619918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010001064022722999310000100101003610036100361003610036
100241003575000619918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010001364022722999310000100101003610036100361003610036
1002410035750005969918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010000064022722999310000100101003610036100361003610036
100241003575000619918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010000064022722999310000100101003610036100361003610036
100241003575000619918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010000064022722999310000100101003610036100361003610036
100241003575000619918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010000064022722999310000100101003610036100361003610036
100241003575000619918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010000064022722999310000100101003610036100361003610036
1002410035750005369918251001010010100106472464969551003510035867838754100101002030020100351041110021109101001010010001064022722999310000100101003610036100361003610036

Test 3: Latency 1->3

Chain cycles: 1

Code:

  cinc x0, x1, hi
  tst x0, 1
  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03l1i tlb fill (04)1e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202042003515000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000001310128112004420100101002003620036200362003620036
202042003515000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000021001310128111999220100101002003620036200362003620036
202042003515000061199262520200202002020012976500491695520035200351740631748120200202004020020035104112020110099201001000000001310128111999220100101002003620036200362003620036
202042003515000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000001310128111999220100101002003620036200362003620036
202042003515000061199262520200202002020012976500491695520035200351740631748120200202004020020035104112020110099201001000000061310128111999220100101002003620036200362003620036
202042003515000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000001310128111999220100101002003620036200362003620036
20204200351500525061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000004201471310128111999220100101002003620036200362003620036
202042003515000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000001310128111999220100101002003620036200362003620036
202042003515000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000001001310128111999220100101002003620036200362003620036
202042003515000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000001310128111999220100101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515006119918252002020020200201297297049169552003520035174283175042002020020400202003510411200211092001010000000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297149169552003520035174283175042002020020400202003510411200211092001010000010901270127111999520010100102003620036200362003620036
200242003514906119918252002020020200201297297149169552003520035174283175042002020020400202003510411200211092001010000000001270127111999520010100102003620036200362003620036
20024200351500611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200101000001018001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020400202003510411200211092001010000010601270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020400202003510411200211092001010000000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020400202003510411200211092001010000000011270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297149169552003520035174283175042002020020400202003510411200211092001010000002001270127211999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020400202003510411200211092001010000000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297149169552003520035174283175042002020020400202003510411200211092001010000000001270127111999520010100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  cinc x0, x8, hi
  cinc x1, x8, hi
  cinc x2, x8, hi
  cinc x3, x8, hi
  cinc x4, x8, hi
  cinc x5, x8, hi
  cinc x6, x8, hi
  cinc x7, x8, hi
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267522000006932780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151182162673780018801002674126741267412674126741
8020426740200000282780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741
80204267402000006932780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741
8020426740200000282780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741
80204267402000006932780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180402673780018801002674126741267412674126741
80204267402000106932780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741
80204267402000005032780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741
80204267402000006932780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741
80204267402010005032780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741
80204267402000006932780118801188012447991604923660267402674016679616689801248023224029626740661180201100991008010080100000011151180162673780018801002674126741267412674126741

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9facbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267232000022225800108001080010472059049236262670626706166653166848001080020240020267066611800211091080010800100050204180242670280000800102670726707267072670726707
8002426706200003625800108001080010472059049236262670626706166653166848001080020240020267066611800211091080010800100050202180422670280000800102670726707267072670726707
80024267062000014525800108001080010472059049236262670626706166653166848001080020240020267066611800211091080010800100050202180242670280000800102670726707267072670726707
8002426706200005725800108001080010472059049236262670626706166653166848001080020240020267066611800211091080010800100050202180242670280000800102670726707267072670726707
80024267061990042425800108001080010472059149236262670626706166653166848001080020240020267066611800211091080010800100050202180442670280000800102670726707267072670726707
8002426706199003625800108001080010472059149236262670626706166653166848001080020240020267066611800211091080010800100050204180422670280000800102670726707267072670726707
8002426706200003625800108001080010472059049236262670626706166653166848001080020240020267066611800211091080010800100050202180242670280000800102670726707267072670726707
8002426706200003625800108001080010472059149236262670626706166653166848001080020240020267066611800211091080010800100050204180242670280000800102670726707267072670726707
8002426706200003625800108001080010472059149236262670626706166653166848001080020240020267066611800211091080010800100050202180442670280000800102670726707267072670726707
8002426706200103625800108001080010472059149236262670626706166653166848001080020240020267066611800211091080010800100050203180422670280000800102670726707267072670726707