Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
cinc x0, x0, hi
mov x0, 1 mov x1, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 1.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int alu (97) | 9f | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
1004 | 1035 | 7 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 1 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 7 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 0 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 7 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 0 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 8 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 0 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1082 |
1004 | 1035 | 8 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 1 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 8 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 1 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 7 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 0 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 8 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 1 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 7 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 1 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
1004 | 1035 | 8 | 61 | 917 | 25 | 1000 | 1000 | 1000 | 62250 | 0 | 1035 | 1035 | 805 | 3 | 882 | 1000 | 1000 | 3000 | 1035 | 104 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 73 | 1 | 27 | 1 | 1 | 990 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
Code:
cinc x0, x0, hi
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0035
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | a9 | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 10035 | 75 | 0 | 0 | 9 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10204 | 10035 | 75 | 0 | 0 | 0 | 251 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10172 |
10204 | 10035 | 75 | 0 | 0 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 4 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10204 | 10035 | 75 | 0 | 0 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10204 | 10035 | 75 | 0 | 0 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10204 | 10035 | 75 | 0 | 0 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10204 | 10035 | 75 | 0 | 1 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10205 | 10035 | 75 | 0 | 1 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10204 | 10035 | 75 | 0 | 0 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 1 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 0 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
10204 | 10035 | 75 | 0 | 0 | 0 | 61 | 9920 | 25 | 10100 | 10100 | 10100 | 647152 | 0 | 49 | 6955 | 10035 | 10035 | 8656 | 3 | 8732 | 10100 | 10200 | 30200 | 10035 | 102 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 10100 | 1 | 0 | 0 | 710 | 1 | 27 | 1 | 1 | 9992 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
Result (median cycles for code): 1.0035
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 1e | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 10035 | 75 | 0 | 0 | 0 | 441 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 0 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 61 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 2 | 0 | 1 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 61 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 1 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 61 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 1 | 3 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 596 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 0 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 61 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 0 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 61 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 0 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 61 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 0 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 61 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 0 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
10024 | 10035 | 75 | 0 | 0 | 0 | 536 | 9918 | 25 | 10010 | 10010 | 10010 | 647246 | 49 | 6955 | 10035 | 10035 | 8678 | 3 | 8754 | 10010 | 10020 | 30020 | 10035 | 104 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10010 | 0 | 0 | 1 | 0 | 640 | 2 | 27 | 2 | 2 | 9993 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
Chain cycles: 1
Code:
cinc x0, x1, hi tst x0, 1
mov x0, 1 mov x1, 2 mov x2, 3
(non-fused SUB/CBNZ loop)
Result (median cycles for code, minus 1 chain cycle): 1.0035
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | 1e | 3a | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst int alu (97) | 9f | l1d tlb miss (a1) | l1d cache writeback (a8) | a9 | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 0 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 20044 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 2 | 1 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 0 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 0 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 0 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 0 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 0 | 0 | 6 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 0 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 525 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 42 | 0 | 147 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 0 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 1 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
20204 | 20035 | 150 | 0 | 0 | 0 | 61 | 19926 | 25 | 20200 | 20200 | 20200 | 1297650 | 1 | 49 | 16955 | 20035 | 20035 | 17406 | 3 | 17481 | 20200 | 20200 | 40200 | 20035 | 104 | 1 | 1 | 20201 | 100 | 99 | 20100 | 10000 | 0 | 0 | 0 | 0 | 1310 | 1 | 28 | 1 | 1 | 19992 | 20100 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
Result (median cycles for code, minus 1 chain cycle): 1.0035
retire uop (01) | cycle (02) | 03 | 1e | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst int alu (97) | 9f | l1d tlb access (a0) | l1d cache writeback (a8) | a9 | ac | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 0 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 0 | 0 | 0 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 1 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 1 | 0 | 9 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 149 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 1 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 0 | 0 | 0 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 0 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 1 | 0 | 180 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 0 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 1 | 0 | 6 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 0 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 0 | 0 | 0 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 0 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 0 | 0 | 0 | 1 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 1 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 0 | 2 | 0 | 0 | 1270 | 1 | 27 | 2 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 0 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 0 | 0 | 0 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
20024 | 20035 | 150 | 0 | 61 | 19918 | 25 | 20020 | 20020 | 20020 | 1297297 | 1 | 49 | 16955 | 20035 | 20035 | 17428 | 3 | 17504 | 20020 | 20020 | 40020 | 20035 | 104 | 1 | 1 | 20021 | 10 | 9 | 20010 | 10000 | 0 | 0 | 0 | 0 | 0 | 1270 | 1 | 27 | 1 | 1 | 19995 | 20010 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
Count: 8
Code:
cinc x0, x8, hi cinc x1, x8, hi cinc x2, x8, hi cinc x3, x8, hi cinc x4, x8, hi cinc x5, x8, hi cinc x6, x8, hi cinc x7, x8, hi
mov x8, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3342
retire uop (01) | cycle (02) | 03 | 18 | 19 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80204 | 26752 | 200 | 0 | 0 | 0 | 693 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 2 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 0 | 0 | 28 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 0 | 0 | 693 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 0 | 0 | 28 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 0 | 0 | 693 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 40 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 1 | 0 | 693 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 0 | 0 | 503 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 0 | 0 | 693 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 201 | 0 | 0 | 0 | 503 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
80204 | 26740 | 200 | 0 | 0 | 0 | 693 | 27 | 80118 | 80118 | 80124 | 479916 | 0 | 49 | 23660 | 26740 | 26740 | 16679 | 6 | 16689 | 80124 | 80232 | 240296 | 26740 | 66 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 80100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 26737 | 80018 | 80100 | 26741 | 26741 | 26741 | 26741 | 26741 |
Result (median cycles for code divided by count): 0.3338
retire uop (01) | cycle (02) | 03 | 19 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | ac | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80024 | 26723 | 200 | 0 | 0 | 222 | 25 | 80010 | 80010 | 80010 | 472059 | 0 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 4 | 18 | 0 | 2 | 4 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 200 | 0 | 0 | 36 | 25 | 80010 | 80010 | 80010 | 472059 | 0 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 2 | 18 | 0 | 4 | 2 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 200 | 0 | 0 | 145 | 25 | 80010 | 80010 | 80010 | 472059 | 0 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 2 | 18 | 0 | 2 | 4 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 200 | 0 | 0 | 57 | 25 | 80010 | 80010 | 80010 | 472059 | 0 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 2 | 18 | 0 | 2 | 4 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 199 | 0 | 0 | 424 | 25 | 80010 | 80010 | 80010 | 472059 | 1 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 2 | 18 | 0 | 4 | 4 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 199 | 0 | 0 | 36 | 25 | 80010 | 80010 | 80010 | 472059 | 1 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 4 | 18 | 0 | 4 | 2 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 200 | 0 | 0 | 36 | 25 | 80010 | 80010 | 80010 | 472059 | 0 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 2 | 18 | 0 | 2 | 4 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 200 | 0 | 0 | 36 | 25 | 80010 | 80010 | 80010 | 472059 | 1 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 4 | 18 | 0 | 2 | 4 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 200 | 0 | 0 | 36 | 25 | 80010 | 80010 | 80010 | 472059 | 1 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 2 | 18 | 0 | 4 | 4 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |
80024 | 26706 | 200 | 1 | 0 | 36 | 25 | 80010 | 80010 | 80010 | 472059 | 1 | 49 | 23626 | 26706 | 26706 | 16665 | 3 | 16684 | 80010 | 80020 | 240020 | 26706 | 66 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 80010 | 0 | 0 | 5020 | 3 | 18 | 0 | 4 | 2 | 26702 | 80000 | 80010 | 26707 | 26707 | 26707 | 26707 | 26707 |