Firestorm: STRB (register) measurements

Code:

  strb w0, [x6, x7]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	552	4	1	1	0	1	17	1	0	1	539	16	16	1	25	1000	1000	1000	23028	1	554	554	376	3	410	1000	1000	3000	554	553	1	1	1001	1000	1000	1015	14	44	0	0	1016	0	0	18	1002	16	44	14	0	73	1	16	1	1	560	1000	553	564	555	555	555
1004	554	4	1	0	1	1	17	1	0	1	539	16	16	4	25	1000	1000	1000	23004	1	554	552	367	3	410	1000	1000	3000	554	551	1	1	1001	1000	1000	1015	14	44	0	0	1016	1	2	17	1002	16	44	14	1	73	1	16	1	1	551	1000	555	555	555	555	555
1004	553	4	1	1	1	0	19	1	0	1	539	16	16	4	25	1000	1000	1000	22908	0	564	554	365	3	412	1000	1000	3000	552	554	1	1	1001	1000	1000	1014	15	44	0	0	1016	0	1	18	1002	16	44	14	0	73	1	16	1	1	550	1000	564	555	555	555	555
1004	554	4	1	1	1	1	17	1	0	1	539	16	16	1	25	1000	1000	1000	22933	1	553	554	367	3	412	1000	1000	3000	554	563	1	1	1001	1000	1000	1015	15	44	0	2	1016	0	1	18	1002	16	44	14	0	73	1	16	1	1	551	1000	555	553	553	565	565
1004	554	4	1	1	1	0	22	0	0	1	537	16	16	2	25	1000	1000	1000	23028	1	554	552	367	3	410	1000	1000	3000	554	554	1	1	1001	1000	1000	1015	15	44	0	0	1016	0	2	16	1002	16	43	14	0	73	1	16	1	1	560	1000	555	555	555	553	552
1004	551	4	1	1	0	1	18	1	0	1	548	16	16	5	25	1000	1000	1000	23004	1	554	552	367	3	410	1000	1000	3000	554	552	1	1	1001	1000	1000	1016	15	44	0	0	1016	0	1	17	1002	16	43	14	2	73	1	16	1	1	551	1000	555	555	555	553	553
1004	552	4	1	1	0	0	17	1	0	1	537	16	16	1	25	1000	1000	1000	23028	1	554	552	367	3	410	1000	1000	3000	554	554	1	1	1001	1000	1000	1014	15	44	0	0	1016	0	2	16	1002	16	44	14	2	73	1	16	1	1	551	1000	554	553	553	565	555
1004	554	4	1	0	0	1	19	1	0	1	537	16	16	2	25	1000	1000	1000	23028	1	563	554	365	3	412	1000	1000	3000	563	554	1	1	1001	1000	1000	1015	14	44	0	2	1016	0	1	17	1002	16	44	14	2	73	1	16	1	1	551	1000	555	555	555	555	555
1004	553	4	1	1	0	1	19	1	0	1	537	16	16	5	25	1000	1000	1000	23487	1	552	554	366	3	412	1000	1000	3000	553	554	1	1	1001	1000	1000	1014	15	44	0	0	1016	0	0	16	1002	16	43	14	0	73	1	16	1	1	549	1000	553	553	565	555	555
1004	554	4	1	0	0	0	20	0	0	1	539	16	16	1	25	1000	1000	1000	23028	1	554	554	376	3	411	1000	1000	3000	563	554	1	1	1001	1000	1000	1014	15	44	0	1	1016	0	0	17	1002	16	44	14	2	73	1	16	1	1	551	1000	554	553	553	555	555

Count: 8

Code:

  strb w0, [x6, x7]
  strb w0, [x6, x7]
  strb w0, [x6, x7]
  strb w0, [x6, x7]
  strb w0, [x6, x7]
  strb w0, [x6, x7]
  strb w0, [x6, x7]
  strb w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40043	300	0	0	7	0	40028	16	0	1	25	80100	100	80000	100	80006	500	1839474	1	49	36962	40042	40042	29961	7	29995	80106	200	80016	200	240048	40042	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	2	80002	0	42	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40043	40041	40041	40041
80204	40042	300	0	0	3	0	40028	0	16	0	25	80100	100	80000	100	80006	500	1839474	1	49	36970	40042	40040	29961	7	29994	80106	200	80016	200	240048	40042	32026	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	2	80002	2	42	1	1	1	5118	0	16	0	40039	4	80000	100	40043	40043	40041	40044	40041
80204	40043	300	0	0	0	0	40029	0	16	0	25	80100	100	80000	100	80006	500	1839378	1	49	36963	40042	40043	29959	7	29995	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80000	0	0	2	80000	2	42	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40043	40041	40043	40044
80204	40042	300	0	0	0	0	40025	16	16	1	25	80100	100	80000	100	80006	500	1839378	1	49	36963	40042	40042	29962	7	29995	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80000	0	0	0	80002	2	0	1	1	1	5118	0	16	0	40037	0	80000	100	40041	40043	40043	40043	40043
80204	40042	300	0	0	3	0	40031	0	16	0	25	80100	100	80000	100	80007	500	1839503	1	49	36960	40043	40043	29961	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80202	100	99	100	80000	100	80000	100	80000	42	1	80002	0	0	2	80002	2	42	1	1	1	5118	0	16	0	40039	0	80000	100	40041	40041	40043	40043	40041
80204	40042	299	0	0	3	0	40029	0	16	0	25	80100	100	80000	100	80006	500	1839378	1	49	36962	40040	40042	29962	7	29995	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80000	0	0	2	80002	0	0	1	1	1	5118	0	16	0	40037	0	80000	100	40044	40043	40043	40041	40041
80204	40040	299	0	0	3	1	40030	0	16	0	25	80100	100	80000	100	80006	500	1839474	1	49	36962	40040	40042	29959	7	29994	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	1	0	2	80002	2	42	1	1	1	5118	0	17	0	40039	0	80000	100	40041	40043	40043	40044	40041
80204	40042	300	0	0	0	0	40028	16	0	1	25	80100	100	80000	100	80006	500	1840031	1	49	36962	40040	40054	29959	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	0	2	80002	2	0	1	1	1	5118	0	16	0	40037	0	80000	100	40044	40044	40041	40043	40043
80204	40042	300	0	0	3	1	40025	0	0	1	25	80100	100	80000	100	80006	500	1839474	1	49	36960	40042	40042	29973	7	29994	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	0	80000	0	42	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40041	40043	40043	40043
80204	40042	300	0	0	0	1	40027	0	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36962	40042	40042	29961	7	29994	80106	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	5	80002	0	42	1	1	1	5118	0	16	0	40040	0	80000	100	40043	40043	40041	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	0	0	0	0	0	3	0	0	0	1	40044	16	16	3	25	80010	10	80000	10	80000	50	1839836	1	49	36979	40059	40059	29993	3	30030	80010	20	80000	20	240000	40050	40053	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	0	0	8	80000	16	36	14	2	5020	0	16	16	12	12	40049	0	80000	10	40060	40052	40059	40053	40059
80024	40052	300	1	0	1	1	0	1	0	0	0	17	1	0	0	1	40039	16	16	8	25	80010	10	80000	10	80000	50	1839836	1	49	36979	40059	40059	29993	3	30027	80010	20	80000	20	240000	40053	40058	1	1	80021	10	9	10	80000	10	80000	10	80016	15	36	2	1	80016	0	1	20	80002	16	36	14	1	5020	0	11	16	13	13	40055	0	80000	10	40051	40059	40052	40060	40052
80024	40061	300	1	0	0	0	0	1	0	0	0	17	1	0	0	1	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40040	40042	29977	3	30030	80010	20	80000	20	240000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	0	80016	0	3	17	80002	16	34	14	2	5020	0	13	16	13	12	40055	20	80000	10	40048	40048	40059	40053	40059
80024	40059	299	1	0	1	0	0	0	0	0	0	19	1	0	0	1	40041	16	16	6	25	80010	10	80000	10	80000	50	1839932	1	49	36979	40058	40059	29994	3	30032	80010	20	80000	20	240000	40052	40059	1	1	80021	10	9	10	80000	10	80000	10	80016	16	36	0	1	80016	0	1	20	80002	16	36	14	0	5020	0	12	16	12	12	40048	20	80000	10	40061	40059	40051	40060	40051
80024	40059	300	1	0	1	1	0	0	0	0	0	17	0	0	0	1	40045	16	16	1	25	80010	10	80000	10	80000	50	1840220	1	49	36972	40049	40052	29988	3	30037	80010	20	80000	20	240000	40057	40050	1	1	80021	10	9	10	80000	10	80000	10	80015	15	34	2	0	80016	0	0	20	80002	16	0	14	0	5020	0	14	16	12	13	40049	0	80000	10	40059	40053	40058	40053	40058
80024	40058	300	1	0	0	1	0	1	0	0	0	18	1	0	0	1	40042	16	16	5	25	80010	10	80000	10	80000	50	1840220	1	49	36972	40059	40050	29985	3	30039	80010	20	80000	20	240000	40059	40059	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	1	80016	0	0	18	80000	14	36	14	1	5020	0	12	16	13	13	40058	0	80000	10	40053	40058	40053	40061	40048
80024	40050	299	1	0	1	1	0	1	0	0	0	18	1	0	0	1	40046	16	16	5	25	80010	10	80000	10	80000	50	1840220	1	49	36972	40051	40052	29987	3	30041	80010	20	80000	20	240000	40061	40052	1	1	80021	10	9	10	80000	10	80000	10	80016	15	36	2	2	80016	0	1	20	80002	16	36	14	1	5020	1	10	16	12	12	40055	0	80000	10	40061	40048	40051	40060	40051
80024	40059	300	1	0	0	0	0	0	0	0	0	14	1	0	0	1	40043	16	16	5	25	80010	10	80000	10	80000	50	1840268	1	49	36972	40051	40052	29987	3	30038	80010	20	80000	20	240000	40058	40051	1	1	80021	10	9	10	80000	10	80000	10	80075	14	36	0	1	80016	9	2	17	80002	16	36	14	0	5020	0	11	16	11	11	40044	0	80000	10	40054	40060	40053	40061	40053
80024	40047	299	1	0	1	1	0	1	0	0	0	14	1	0	0	1	40046	16	16	5	25	80010	10	80000	10	80000	50	1840246	1	49	36978	40053	40058	29994	3	30027	80010	20	80000	20	240000	40049	40052	1	1	80021	10	9	10	80000	10	80000	10	80014	15	36	0	0	80016	0	1	17	80002	16	34	14	2	5020	0	12	16	13	12	40055	0	80000	10	40060	40053	40052	40060	40061
80024	40199	311	1	0	0	0	0	1	0	0	0	21	0	0	0	1	40046	16	16	1	115	80070	10	80000	10	80108	50	1840220	1	49	37391	40049	40052	29988	3	30037	80010	20	80000	20	240000	40057	40467	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	1	80016	0	1	835	80062	16	36	14	3	5115	0	13	89	20	13	41125	0	80000	10	41242	41163	41307	41170	41305

STRB (register)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations