Firestorm: STLXR (32-bit) measurements

Code:

  stlxr w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 50.674

Integer unit issues: 0.000

Load/store unit issues: 50.674

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	22	23	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	64	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	37993	285	0	1998	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5937	24394	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2062	2	2	37909	1000	38018	37994	37994	37994	37994
1004	37993	285	0	1998	1	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5947	24397	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2063	2	2	37909	1000	37996	37994	37994	37994	37994
1004	37993	285	0	1998	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5949	24406	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2057	2	2	37909	1000	37994	37994	37994	37994	37994
1004	37993	285	0	1998	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5947	24397	87814	91533	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2055	2	2	37909	1000	37994	37994	37994	37994	37994
1004	37993	284	0	1998	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5949	24406	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2060	2	2	37909	1000	37994	37994	37994	37994	37994
1004	37993	285	0	1998	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5937	24394	87814	91439	182878	38031	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2057	2	2	37909	1000	37994	37994	37994	37994	37994
1004	37993	285	0	1998	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5943	24395	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2063	2	2	37909	1000	37994	37994	37994	37994	37994
1004	37993	284	0	2004	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5949	24402	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2057	2	2	37909	1000	37994	37994	37994	37994	37994
1004	37993	285	0	1998	0	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5945	24400	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44953	44965	44965	1998	44965	1000	1000	16591	2	2055	2	2	37909	1000	37994	37994	37994	37994	37994
1004	37993	285	0	1998	1	0	37978	7267	50674	50674	87814	1003234	1	1000	49	34913	37993	37993	13140	5947	24400	87814	91439	182878	37993	37993	1001	1	1001	1000	1000	44965	44965	44965	1998	44965	1000	1000	16591	2	2063	2	2	37909	1000	37994	37994	37994	37994	37994

Test 2: throughput

Code:

  stlxr w0, w1, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.9167

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	c2	cd	cf	d5	map dispatch bubble (d6)	d8	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20209	389236	2916	5	6	5	0	7	5	0	0	3	20910	0	849	1	0	0	536	167	252	389183	584	0	69476	558500	298924	259576	788798	697483	12744591	11717744	0	10000	0	49	386065	389126	389250	83530	59081	181172	1486258	794497	778668	794496	1557208	389250	389253	10001	1	20201	100	99	100	10000	10100	10000	100	230531	9	36633	298	0	659	229834	10	1	834	72	19998	230551	10000	1528	0	0	209481	65	10975	0	0	61	74	389194	291426	0	10000	10100	389241	389251	389129	389129	389253
20204	389128	2915	1	7	0	0	7	1	0	0	0	20115	0	791	2	0	0	816	162	160	389236	626	0	69280	558504	298927	259576	788800	697489	12744667	11717733	0	10000	0	49	386049	389127	389249	83467	59210	181304	1486282	794472	778664	794473	1557328	389252	389128	10001	1	20201	100	99	100	10000	10100	10000	100	230592	18	32787	285	0	724	229856	6	0	985	94	20028	230569	10000	1712	0	0	209482	69	10970	0	0	41	70	389069	291426	0	10000	10100	389253	389130	389251	389128	389252
20204	389252	2915	2	10	0	0	10	0	0	0	0	20160	0	842	1	0	0	544	183	148	389114	608	0	69402	558500	298924	259576	788771	697486	12744631	11717702	0	10000	14	49	386047	389129	389127	83528	59203	181171	1486260	794497	778665	794498	1557330	389127	389129	10001	1	20201	100	99	100	10000	10100	10000	100	230535	2	32434	301	0	718	229859	9	0	952	86	20010	230574	10000	1408	2	0	209481	69	10975	0	0	57	78	389190	291423	0	10000	10100	389251	389253	389251	389131	389129
20204	389250	2915	2	10	0	0	10	0	0	0	0	20243	0	818	1	0	0	776	175	232	389235	574	0	69280	558516	298927	259577	788772	697487	12744578	11716922	0	10000	28	49	386173	389253	389253	83531	59206	181174	1486257	794504	778665	794471	1557326	389128	389250	10001	1	20201	100	99	100	10000	10100	10000	100	230587	0	39945	215	0	721	229839	22	0	897	88	20028	230559	10000	1384	4	0	209480	70	10970	0	0	65	78	389067	291425	0	10000	10100	389130	389252	389129	389305	389253
20204	389129	2916	2	10	2	0	10	0	0	0	0	20162	0	856	2	0	0	608	155	272	389234	615	0	69430	558524	298926	259576	788778	697488	12744706	11717689	1	10000	0	49	386047	389127	389127	83464	59177	181297	1486261	794497	778669	794470	1557212	389252	389128	10001	1	20201	100	99	100	10000	10100	10000	100	230532	12	35700	196	0	679	229861	3	0	864	90	20007	230608	10000	1552	2	0	209479	66	10972	0	0	65	78	389190	291438	0	10000	10100	389128	389129	389253	389128	389253
20204	389249	2978	2	6	2	0	6	0	0	0	0	20093	0	844	1	0	0	744	157	212	389113	563	0	69404	558502	298925	259577	788771	697487	12744740	11716965	0	10000	0	49	386047	389250	389130	83464	59203	181173	1486284	794496	778665	794497	1557330	389260	389128	10001	1	20201	100	99	100	10000	10100	10000	100	230552	12	33346	309	0	673	229858	5	2	849	72	20016	230595	10000	1432	2	0	209479	70	10975	1896	4	60	72	389372	291453	0	10000	10100	389137	389251	389128	389251	389130
20204	389206	3135	3	7	2	0	7	0	1	0	0	20253	0	819	0	2	0	720	189	116	389235	569	0	69402	558516	298926	259576	788770	697486	12744703	11716973	0	10000	0	49	386047	389252	389254	83467	59206	181292	1486391	794474	778604	794500	1557208	389129	389254	10001	1	20201	100	99	100	10000	10100	10000	100	230587	6	32096	371	0	685	229863	11	0	928	52	20031	230624	10000	1344	2	0	209479	70	10978	0	0	65	78	389079	291423	0	10000	10100	389128	389129	389129	389129	389253
20204	389251	2915	2	5	0	2	10	2	0	0	0	20124	0	857	0	0	2	576	196	396	389113	523	0	69402	558516	298935	259576	788803	697486	12744601	11716917	0	10000	0	49	386170	389250	389252	83527	59255	181295	1486256	794497	778604	794473	1557330	389128	389131	10001	1	20201	100	99	100	10000	10100	10000	100	230544	8	31681	241	0	660	229853	5	0	910	62	20016	230529	10000	1280	0	0	209479	66	10975	0	0	65	78	389067	291428	0	10000	10100	389253	389255	389254	389129	389254
20204	389316	2915	2	9	2	2	12	0	0	0	0	20154	0	843	0	0	2	512	174	152	389112	603	0	69280	558514	298924	259577	788801	697486	12744605	11716871	0	10000	0	49	386048	389127	389251	83530	59080	181168	1486282	794478	778664	794474	1557200	389249	389250	10001	1	20201	100	99	100	10000	10100	10000	100	230652	4	36087	291	0	694	229867	8	0	929	42	20046	230514	10000	1280	0	0	209483	66	10972	0	0	65	78	389190	291423	0	10000	10100	389252	389215	389303	389253	389128
20204	389128	2915	2	10	0	0	9	0	0	0	0	20217	0	784	0	2	0	584	173	296	389236	618	0	69404	558502	298925	259577	788771	697487	12744711	11717796	0	10000	0	49	386173	389253	389252	83528	59202	181291	1486284	794477	778667	794473	1557208	389250	389127	10001	1	20201	100	99	100	10000	10100	10000	100	230479	2	35532	326	0	648	229848	6	2	890	92	20016	230607	10000	1392	8	10	209578	105	11071	0	0	65	78	389068	291424	0	10000	10100	389128	389254	389250	389129	389131

1000 unrolls and 10 iterations

Result (median cycles for code): 38.9945

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20029	389954	2921	0	0	0	0	0	0	0	20333	0	809	1	0	456	113	228	389934	537	0	70099	550200	290544	259657	760249	697567	12689430	11764772	1	10000	0	49	386869	0	389937	389937	70811	59889	188857	1457812	760815	759164	760811	1518322	389949	389939	10001	1	20021	10	9	10	10000	10010	10000	10	230707	11	38858	294	0	725	229945	9	0	888	32	20013	230622	10000	7	1288	0	1	0	200997	49	10976	45	47	389896	289803	10000	10010	390253	389958	389948	389950	389957
20024	389957	2920	0	1	1	0	0	0	0	20215	7	811	1	0	632	128	252	389937	599	0	70099	550202	290544	259666	760248	697574	12689803	11765239	0	10000	0	49	386866	0	389945	389946	70820	59889	188851	1457824	760816	759159	760816	1518354	389939	389949	10001	1	20021	10	9	10	10000	10010	10000	10	230642	7	32069	308	0	675	229936	11	0	890	82	20013	230613	10000	0	1488	0	0	0	201001	48	10976	46	43	389890	289794	10000	10010	389958	389949	389953	389951	389949
20024	389948	2921	0	0	0	0	0	0	0	20289	0	836	1	0	496	122	124	389921	647	4	70100	550216	290552	259664	760261	697574	12689915	11765184	1	10000	0	49	386876	3	389955	389955	70815	59889	188864	1457837	760822	759171	760820	1518354	389945	44	10001	1	20021	10	9	10	10000	10010	10000	10	230747	7	35566	306	0	726	229973	5	0	966	46	20017	230698	10000	7	1472	1	1	2	200999	51	10978	46	48	389876	289796	10000	10010	389959	389977	389948	389940	389938
20024	389937	2921	0	0	0	0	0	0	0	20246	0	853	1	0	632	126	112	389931	533	3	70090	550218	290559	259665	760244	697566	12689438	11764785	0	10000	0	49	386857	0	389936	389950	70828	59895	188856	1457826	760820	759176	760823	1518356	389955	44	10001	1	20021	10	9	10	10000	10010	10000	10	230732	8	39603	294	0	685	229925	4	1	896	90	20020	230601	10000	0	1328	0	0	0	200996	48	10978	47	48	389885	289802	10000	10010	389971	389947	389945	389958	389989
20024	389944	2921	0	1	0	0	1	0	0	20166	7	794	1	0	704	112	308	389941	704	3	70088	550216	290554	259665	760252	697575	12689859	11765087	1	10000	14	49	386869	0	389937	389937	70816	59906	188857	1457808	760813	759281	760814	1518328	389940	389941	10001	1	20021	10	9	10	10000	10010	10000	10	230699	16	34116	322	0	745	229962	9	1	897	42	20023	230673	10000	7	1360	1	1	0	200999	48	10976	46	49	389885	289793	10000	10010	389958	389945	389937	389948	389948
20024	389947	2921	0	0	0	0	0	0	0	20227	0	841	2	0	728	117	224	389978	715	0	70099	550204	290560	259657	760244	697567	12689436	11764712	0	10000	0	49	386865	0	389956	389948	70816	59898	188846	1457823	760818	759164	760823	1518344	389937	389950	10001	1	20021	10	9	10	10000	10010	10000	10	230729	10	32797	272	0	643	229962	6	2	886	114	20038	230625	10000	7	1432	1	0	0	201000	48	10974	47	48	389937	289796	10000	10010	390234	389963	389949	389946	389957
20024	390030	2921	0	1	1	0	1	0	0	20188	7	808	1	0	632	112	220	389934	546	0	70100	550202	290545	259657	760242	697567	12689403	11764700	0	10000	0	49	386857	0	389949	389948	70809	59898	188858	1457936	760818	759177	760812	1518342	389950	389949	10001	1	20021	10	9	10	10000	10010	10000	10	230775	8	29499	286	0	701	229922	9	0	872	84	20007	230625	10000	0	1368	0	0	0	200997	48	10978	46	48	389878	289796	10000	10010	389982	389957	389942	389937	389997
20024	389951	2921	0	0	1	0	0	0	0	20187	7	811	2	0	728	110	136	389933	641	4	70099	550218	290566	259665	760248	697574	12689754	11765196	0	10000	0	49	386864	0	389945	389946	70821	59888	188856	1457824	760828	759174	760823	1518352	389958	44	10002	1	20021	10	9	10	10000	10010	10000	10	230665	7	40148	340	0	706	229961	12	0	921	50	20026	230632	10000	7	1568	1	1	0	200999	48	10976	47	48	389885	289803	10000	10010	389962	389957	389957	389945	389947
20024	389945	2920	0	1	0	0	0	0	0	20222	0	814	1	0	696	96	180	389922	460	0	70134	550228	290565	259657	760244	697567	12689507	11764719	0	10000	0	49	386857	0	389936	389948	70814	59889	188859	1457818	760813	759160	760818	1518340	389937	389939	10001	1	20021	10	9	10	10000	10010	10000	10	230685	8	34284	266	0	710	229939	7	0	952	66	20010	230560	10000	0	1504	0	1	0	200997	49	10977	46	43	389876	289793	10000	10010	389947	389952	389937	389949	389939
20024	389937	2920	0	1	1	0	1	0	0	20321	0	856	1	0	744	105	216	389923	610	0	70100	550202	290545	259664	760252	697567	12689453	11764711	0	10000	0	49	386869	0	389947	389951	70828	59906	188859	1457825	760820	759170	760819	1518324	389950	389937	10001	1	20021	10	9	10	10000	10010	10000	10	230678	7	34645	264	9	670	229950	7	1	888	42	20017	230643	10000	7	1616	1	3	0	201000	48	10970	46	49	389895	289797	10000	10010	389983	389957	389948	389937	389949

Test 3: throughput

Code:

  stlxr w0, w1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.0115

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10205	381800	2901	1	0	2	114	115	34902	10486	1	0	0	383927	0	70276	529272	10697	518575	10697	915715	54384	10461754	0	10000	49	377030	0	380154	380119	130429	59947	248975	926412	19100	938418	19100	1876836	380143	380120	10001	1	10201	100	99	100	10000	100	10000	100	458882	15	458868	0	0	458882	0	1	20012	458868	10000	14	10000	1	1	10	172637	1	133	11082	131	131	380051	1197	10000	100	380119	380119	380119	380119	380119
10204	380118	2848	1	1	1	0	0	19998	14	1	0	33	380104	2	70276	529270	10697	518577	10697	915717	54384	10462140	0	10000	49	377038	0	380118	380118	130436	59951	248982	926414	19100	938418	19100	1876836	380147	380118	10001	1	10202	100	99	100	10000	100	10000	100	458885	14	458890	0	1	458882	0	0	20100	458867	10000	14	10000	1	0	10	172651	1	137	11182	131	131	380267	1197	10000	100	380119	380119	380119	380119	380119
10204	380120	2847	1	1	0	0	0	19998	14	0	0	182	380103	0	70276	529271	10697	518575	10697	915717	54384	10462141	1	10000	49	377039	0	380118	380118	130437	59951	248998	926413	19100	938418	19100	1876836	380125	380118	10001	1	10201	100	99	100	10000	100	10000	100	458882	14	458867	0	0	458882	0	0	20012	458868	10000	14	10000	1	0	10	172651	1	137	11081	130	130	380051	1197	10000	100	380141	380119	380119	380119	380119
10204	380118	2848	1	0	1	0	0	19998	14	1	0	183	380103	0	70276	529274	10697	518574	10697	915716	54384	10462146	0	10000	49	377038	0	380118	380120	130436	59961	248990	926414	19100	938933	19100	1876836	380119	380118	10001	1	10201	100	99	100	10000	100	10000	100	458882	14	458868	0	0	458881	0	1	20012	458867	10000	14	10000	1	2	10	172637	1	131	11068	130	130	380051	1197	10000	100	380119	380120	380119	380119	380119
10204	380118	2847	1	1	1	0	0	19998	14	0	0	182	380103	0	70277	529271	10697	518574	10699	915717	54384	10463683	0	10000	49	377038	0	380118	380118	130436	59944	248994	926414	19100	938418	19100	1876836	380150	380118	10001	1	10201	100	99	100	10000	100	10000	100	458882	15	458867	0	0	458881	0	1	20012	458868	10000	14	10000	1	0	10	172636	1	130	11074	132	132	380059	1197	10000	100	380119	380119	380119	380119	380119
10204	380118	2847	1	1	0	0	0	20040	14	1	0	185	380103	3	70276	529271	10697	518576	10697	915717	54384	10462141	1	10000	49	377038	0	380118	380228	130409	59951	248998	926474	19100	938418	19100	1876836	380120	380118	10001	1	10201	100	99	100	10000	100	10000	100	458882	15	458868	0	1	458882	0	2	20012	458867	10000	14	10000	1	2	10	172651	1	130	11079	131	131	380053	1197	10000	100	380119	380121	380133	380130	380120
10204	380118	2847	1	1	1	0	0	20025	14	1	0	185	380103	0	70278	529270	10697	518575	10697	915717	54384	10462151	0	10000	49	377038	0	380118	380118	130436	59954	248984	926414	19100	938418	19100	1876836	380132	380126	10001	1	10201	100	99	100	10000	100	10000	100	458883	15	458867	0	1	458881	1	1	20021	458868	10000	14	10000	1	0	10	172639	1	131	11081	130	130	380051	1197	10000	100	380119	380119	380119	380119	380119
10204	380122	2847	1	1	0	0	0	19998	14	0	0	183	380103	0	70276	529270	10697	518577	10697	915717	54384	10462141	0	10000	49	377039	0	380118	380118	130429	59964	248990	926414	19100	938418	19100	1876836	380133	380118	10001	1	10201	100	99	100	10000	100	10000	100	458882	15	458878	0	1	458882	0	2	20012	458867	10000	14	10000	1	0	10	172639	1	131	11082	131	131	380051	1197	10000	100	380119	380119	380119	380119	380119
10204	380118	2848	1	1	0	0	0	19998	14	1	0	183	380103	0	70276	529272	10697	518574	10697	915662	54384	10462148	0	10000	49	377038	0	380118	380118	130437	59951	248991	926434	19100	938443	19100	1876886	380126	380117	10001	1	10201	100	99	100	10000	100	10000	100	458882	15	458867	0	0	458882	0	0	20012	458867	10000	14	10000	1	1	10	172638	1	130	11064	130	130	380048	1197	10000	100	380118	380116	380116	380117	380131
10204	380115	2847	1	0	0	0	0	19998	14	0	0	180	380102	13	70271	529274	10697	518574	10699	915740	54384	10462434	0	10000	49	377035	0	380115	380115	130444	59953	248989	926435	19100	938443	19100	1876886	380135	380130	10001	1	10201	100	99	100	10000	100	10000	100	458883	15	458868	0	2	458882	0	1	20012	458868	10000	14	10000	1	0	10	172638	1	130	11069	130	130	380048	1197	10000	100	380122	380117	380116	380116	380118

1000 unrolls and 10 iterations

Result (median cycles for code): 38.0011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	23	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10025	380019	2848	1	0	1	19998	0	1	0	380004	0	70267	519731	1067	518667	1067	915806	5424	10470750	0	10000	49	376939	0	380019	380054	138355	59947	249345	916874	1910	953891	1910	1907782	380019	380043	10001	1	10021	10	9	10	10000	10	10000	10	458972	15	458971	0	2	458953	0	1	20022	458957	10000	14	10000	1	2	0	169648	48	11080	51	45	379952	117	10000	10	380020	380020	380020	380020	380282
10024	380019	2847	1	1	1	19998	14	0	0	379998	0	70267	519731	1067	518665	1067	915805	5424	10470379	0	10000	49	376933	0	380011	380048	138348	59939	249327	916872	1910	954034	1910	1907786	380013	380016	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169648	50	11176	51	50	379949	117	10000	10	380012	380012	380012	380012	380012
10024	380011	2846	0	0	0	19998	0	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470364	1	10000	49	376931	0	380011	380050	138347	59939	249327	916872	1910	953890	1910	1907782	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458955	10000	0	10000	0	0	0	169650	51	11077	51	43	379992	117	10000	10	380012	380012	380012	380014	380012
10024	380011	2846	0	0	0	20011	0	0	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470364	0	10000	49	376931	0	380050	380050	138351	59947	249329	916872	1910	953891	1910	1907780	380011	380011	10002	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	2	169650	51	11080	44	51	379967	117	10000	10	380012	380012	380012	380013	380012
10024	380012	2847	0	0	0	19998	0	1	0	380004	4	70267	519730	1067	518667	1067	915807	5424	10470692	1	10000	49	376931	0	380011	380019	138348	59941	249333	916872	1910	953891	1910	1907786	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458958	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169650	45	11076	50	51	379944	117	10000	10	380014	380012	380012	380012	380012
10024	380011	2846	0	0	0	19998	0	1	0	379996	0	70267	519732	1067	518665	1067	915805	5424	10470384	0	10000	49	376931	0	380011	380044	138346	59939	249327	916872	1910	953891	1910	1907782	380011	380013	10001	1	10021	10	9	10	10000	10	10000	10	458966	0	458956	0	0	458956	0	0	20206	458956	10000	0	10000	0	0	0	169650	51	11080	43	43	379945	117	10000	10	380012	380012	380012	380012	380012
10024	380011	2847	0	0	0	19998	0	0	0	379997	0	70268	519732	1067	518665	1067	915805	5424	10470502	0	10000	49	376931	0	380012	380019	138348	59942	249331	916872	1910	953890	1910	1907780	380012	380013	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169654	44	11076	51	51	379944	117	10000	10	380012	380012	380012	380012	380012
10024	380011	2847	0	0	0	19998	0	1	0	379996	0	70267	519732	1067	518664	1067	915804	5424	10470364	0	10000	49	376931	0	380016	380028	138348	59947	249335	916872	1910	953890	1910	1907780	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458958	0	2	458956	0	0	19998	458956	10000	0	10000	0	0	0	169650	44	11070	51	43	379945	117	10000	10	380012	380012	380012	380012	380012
10024	380011	2846	0	0	0	19998	0	1	0	380025	0	70269	519732	1067	518665	1067	915805	5424	10470364	0	10000	49	376931	0	380011	380057	138348	59939	249340	916871	1910	954011	1910	1907796	380013	380013	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169649	51	11081	51	43	379944	117	10000	10	380012	380013	380134	380013	380013
10024	380011	2846	0	0	0	19998	0	0	0	380023	0	70267	519732	1067	518665	1067	915805	5424	10470379	0	10000	49	376931	0	380011	380021	138348	59952	249327	916876	1910	953890	1910	1907780	380012	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169648	50	11078	44	50	379944	117	10000	10	380012	380012	380012	380012	380012

STLXR (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations