Firestorm: LDRSB (unsigned offset, 32-bit) measurements

Code:

  ldrsb w0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	0	1	0	0	0	1	22	0	0	3	388	2	7	7	0	25	1000	1000	1000	15597	0	382	403	225	3	240	1000	1000	1000	403	64	1	1	1001	0	1000	1000	0	1021	20	0	1058	0	0	1	61	1040	6	1	59	43	19	0	73	2	16	1	1	378	13	0	5	1000	404	403	403	404	404
1004	381	3	1	0	0	1	0	0	0	0	67	0	0	2	388	0	7	9	19	25	1000	1000	1000	15555	0	382	403	204	3	261	1000	1000	1000	381	85	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	0	1	60	1000	0	1	59	43	19	1	73	1	16	1	1	400	13	13	0	1000	403	404	404	382	404
1004	403	3	1	1	0	0	0	0	0	0	67	0	0	3	367	3	9	7	20	25	1000	1000	1000	15531	0	403	381	204	3	266	1000	1000	1000	403	64	1	1	1001	0	1000	1000	0	1021	20	0	1019	1	0	2	21	1040	6	1	59	43	19	1	73	1	16	1	1	379	13	0	5	1000	404	404	405	403	404
1004	382	3	1	1	1	1	1	1	0	0	67	0	0	0	388	3	0	0	19	25	1000	1000	1000	14456	0	403	402	204	3	261	1000	1000	1000	402	64	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	0	1	60	1040	6	0	19	43	19	0	73	1	16	1	1	400	0	13	5	1000	382	404	404	403	383
1004	403	3	1	1	1	1	0	0	0	0	21	1	0	3	366	3	7	7	19	25	1000	1000	1000	15555	0	403	381	204	3	261	1000	1000	1000	403	64	1	1	1001	0	1000	1000	0	1019	19	0	1059	0	0	1	61	1040	6	0	19	0	19	2	73	1	16	1	1	400	13	13	5	1000	382	382	383	404	404
1004	403	3	1	1	0	1	0	0	0	0	67	0	0	3	388	2	7	0	19	25	1000	1000	1000	15482	0	403	403	225	3	261	1000	1000	1000	403	64	1	1	1001	0	1000	1000	0	1019	20	43	1060	1	0	1	60	1039	0	0	59	43	19	1	73	1	16	1	1	400	13	0	0	1000	404	383	383	382	404
1004	382	3	1	1	1	1	0	0	0	0	21	0	0	3	387	2	7	7	19	25	1000	1000	1000	15526	0	403	403	225	3	261	1000	1000	1000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	0	1	60	1000	6	0	19	43	19	2	73	1	16	1	1	400	0	0	5	1000	404	403	382	404	404
1004	381	3	1	0	1	0	0	0	0	0	76	0	0	3	388	2	7	7	19	25	1000	1000	1000	14533	0	403	382	204	3	260	1000	1000	1000	403	64	1	1	1001	0	1000	1000	0	1019	19	43	1058	0	0	2	61	1000	0	1	58	43	19	0	73	1	16	1	1	401	0	13	0	1000	404	383	404	405	382
1004	404	3	1	1	0	1	0	0	0	0	67	0	0	3	388	0	7	7	19	25	1000	1000	1000	14456	0	403	381	204	3	261	1000	1000	1000	381	85	1	1	1001	0	1000	1000	0	1019	18	0	1058	1	0	1	21	1040	6	1	59	43	19	0	73	1	16	1	1	378	13	13	0	1000	404	382	404	403	403
1004	403	2	1	0	1	0	0	0	0	0	66	0	0	2	369	0	7	7	19	25	1000	1000	1000	14533	0	403	403	225	3	260	1000	1000	1000	403	64	1	1	1001	0	1000	1000	0	1019	21	0	1060	1	0	6	61	1000	0	1	58	0	19	0	73	1	16	1	1	379	0	0	0	1000	404	404	382	403	404

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	0	0	0	0	0	0	0	6	1	0	0	70020	69782	59710	25	40100	30100	10001	30100	10000	616014	3341470	49	66955	0	70051	70051	64650	0	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	0	0	1	10000	1	1	1	1	1	0	2610	2	71	1	1	69823	30006	0	10	0	10000	30100	70055	70055	70036	70055	70055
40204	70055	524	0	0	0	0	0	1	0	1	0	0	0	70039	69788	59716	25	40108	30106	10002	30100	10000	616095	3342542	49	66977	0	70060	70060	64654	0	3	64963	40100	30200	10000	60200	10000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	2610	1	71	1	1	69814	30000	0	13	10	10000	30100	70061	70058	70061	70058	70042
40204	70041	525	1	1	0	0	0	0	0	2	0	0	0	70042	69790	59713	25	40104	30100	10000	30100	10000	616041	3342398	49	66974	0	70054	70035	64650	0	3	64957	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	0	10002	0	0	1	10000	0	1	1	1	0	0	2610	1	71	1	1	69823	30006	0	13	10	10000	30100	70055	70055	70060	70055	70055
40204	70035	525	0	0	0	0	0	0	0	1	0	0	0	70020	69791	59701	25	40108	30106	10002	30100	10000	616095	3341769	49	66980	0	70063	70060	64653	0	3	64944	40296	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	0	2610	1	71	1	1	69814	30003	0	13	0	10000	30100	70036	70055	70055	70052	70052
40204	70054	524	0	0	0	0	0	0	0	0	0	0	0	70020	69791	59719	25	40104	30106	10002	30100	10000	616078	3342542	49	66961	0	70060	70041	64656	0	3	64944	40100	30200	10000	60200	10000	70062	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	0	2610	1	71	1	1	69817	30003	13	10	13	10000	30100	70063	70042	70042	70061	70061
40204	70060	524	1	0	1	1	0	0	0	2	0	0	0	70045	69785	59695	25	40104	30103	10001	30100	10000	616086	3342638	49	66971	0	70054	70054	64650	0	3	64938	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	3	1	10002	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69823	30006	0	13	13	10000	30100	70055	70055	70055	70036	70055
40204	70054	524	0	0	0	0	0	0	0	1	0	0	0	70039	69764	59713	25	40104	30103	10000	30100	10000	616041	3342398	49	66974	0	70054	70054	64650	0	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30000	13	13	0	10000	30100	70061	70061	70061	70061	70061
40204	70060	525	1	0	1	0	0	0	0	1	1	0	0	70042	69785	59713	25	40104	30100	10001	30100	10000	616175	3342398	49	66974	0	70054	70035	64650	0	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	1	0	10001	4	0	1	10000	0	1	0	1	2	0	2610	1	71	1	1	69820	30006	0	13	13	10000	30100	70055	70036	70036	70052	70055
40204	70054	525	0	0	0	0	1	0	0	1	0	0	0	70039	69791	59719	25	40108	30106	10002	30100	10000	616095	3341769	49	66980	0	70060	70041	64637	0	3	65006	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	2645	1	71	1	1	69814	30000	13	10	10	10000	30100	70061	70042	70061	70062	70066
40204	70063	525	1	0	1	0	0	0	0	7	0	0	0	70045	69785	59713	25	40104	30100	10000	30100	10000	616014	3342254	49	66974	0	70054	70054	64647	0	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	1	1	10000	1	1	0	1	1	0	2610	1	71	1	1	69804	30006	13	13	0	10000	30100	70052	70052	70036	70055	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	0	1	0	1	0	1	0	70073	69728	59709	25	40014	30013	10001	30010	10000	616952	3342206	0	49	66970	70050	70050	64665	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10009	0	0	10000	1	1	0	0	0	2520	2	71	3	4	69810	30003	6	6	6	10000	30010	70048	70051	70048	70048	70036
40024	70035	524	1	0	0	0	1	0	0	0	70032	69728	59706	25	40014	30010	10001	30010	10000	616952	3342062	0	49	66970	70050	70050	64668	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	2	71	4	4	69810	30003	6	6	6	10000	30010	70051	70051	70051	70051	70048
40024	70047	525	0	1	1	0	1	0	1	0	70035	69743	59706	38	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70050	70047	64669	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	0	2520	2	71	2	3	69813	30003	9	6	9	10000	30010	70036	70048	70145	70062	70050
40024	70047	525	1	0	0	0	1	0	1	0	70035	69760	59709	25	40014	30013	10001	30010	10000	616952	3342206	0	49	66967	70047	70047	64668	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	1	0	0	0	2520	2	71	4	3	69813	30003	9	6	6	10000	30010	70051	70048	70036	70036	70048
40024	70047	524	0	1	1	0	0	0	1	0	70032	69760	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66955	70047	70050	64665	3	64972	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	0	2520	2	71	3	4	69798	30003	0	6	6	10000	30010	70048	70048	70048	70048	70036
40024	70047	525	0	0	0	0	1	0	1	0	70032	69728	59706	25	40014	30013	10000	30010	10000	617006	3342110	0	49	66967	70047	70050	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	2	71	4	4	69798	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	524	0	0	0	0	1	0	0	0	70032	69728	59771	25	40014	30013	10004	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10065	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	2	71	2	2	69810	30003	6	6	6	10000	30010	70051	70048	70051	70036	70048
40024	70035	525	1	1	1	0	0	0	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3341470	0	49	66967	70050	70050	64668	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	0	2520	2	71	2	2	69810	30003	6	6	6	10000	30010	70048	70048	70048	70036	70048
40024	70047	525	0	0	0	0	1	0	1	0	70032	69760	59706	25	40014	30010	10001	30010	10000	616952	3341470	0	49	66970	70050	70050	64668	3	64972	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	4	71	4	4	69810	30003	6	6	0	10000	30010	70048	70036	70048	70048	70036
40024	70047	525	0	0	0	0	1	0	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616982	3342206	0	49	66955	70050	70035	64653	3	64972	40220	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	0	0	2520	2	71	2	2	69810	30000	6	0	6	10000	30010	70051	70048	70048	70048	70048

Test 3: throughput

Count: 8

Code:

  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26736	201	0	1	61	0	0	0	1	26720	18	4	19	20	25	80100	100	80000	100	80000	500	1167924	1	49	23655	26735	26735	16658	3	16673	80100	200	80000	200	80000	26715	65	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80055	1	0	55	80025	6	1	55	44	5110	1	16	3	3	26712	0	10	0	6	80000	100	26736	26736	26736	26716	26736
80204	26735	200	0	0	61	0	0	0	1	26720	17	0	19	3	25	80100	100	80000	100	80000	500	1169525	0	49	23655	26735	26735	16658	3	16673	80100	200	80000	200	80000	26733	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	59	80055	0	0	25	80025	6	0	25	44	5110	2	16	2	3	26732	0	13	0	6	80000	100	26738	26736	26716	26736	26716
80204	26735	200	0	0	25	0	0	0	1	26789	21	4	0	20	25	80100	100	80000	100	80000	500	1167924	0	49	23655	26735	26735	16636	3	16673	80100	200	80000	200	80000	26735	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	59	80185	19	0	55	80025	6	1	55	44	5110	2	16	2	3	26732	0	13	10	6	80000	100	26736	26736	26716	26736	26736
80204	26735	200	1	0	61	0	0	0	1	26720	17	0	19	19	25	80100	100	80000	100	80000	500	1166334	0	49	23655	26715	26715	16658	3	16673	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	59	80025	0	0	55	80055	6	1	25	44	5110	3	16	4	2	26732	0	10	10	6	80000	100	26738	26736	26717	26716	26736
80204	26735	200	1	0	61	0	0	0	0	26720	17	4	19	20	25	80100	100	80000	100	80000	500	1177584	0	49	23635	26735	26715	16658	3	16693	80100	200	80000	200	80000	26715	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	59	80025	0	0	55	80055	6	1	55	0	5110	4	16	4	2	26732	0	10	10	6	80000	100	26736	26736	26716	26736	26716
80204	26735	200	0	0	25	0	0	0	0	26701	17	4	19	3	25	80100	100	80000	100	80000	500	1166710	1	49	23636	26715	26735	16658	3	16693	80100	200	80000	200	80000	26735	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	59	80055	0	0	54	80055	6	1	55	44	5110	3	16	2	4	26732	0	10	10	6	80000	100	26716	26736	26736	26737	26736
80204	26735	200	0	0	61	0	0	0	1	26720	17	4	19	20	25	80100	100	80000	100	80000	500	1167564	0	49	23655	26715	26715	16638	3	16693	80100	200	80000	200	80000	26735	85	1	1	80201	100	99	100	80000	100	80000	1	100	80000	59	80055	0	0	25	80055	6	1	55	0	5110	5	16	3	1	26732	0	10	10	0	80000	100	26730	26716	26736	26716	26736
80204	26735	200	0	0	61	0	0	0	0	26720	17	4	19	20	25	80100	100	80000	100	80000	500	1167468	1	49	23655	26735	26735	16658	3	16693	80100	200	80000	200	80000	26715	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80055	0	0	55	80025	6	0	25	44	5110	4	16	4	2	26732	0	10	10	0	80000	100	26716	26736	26716	26716	26736
80204	26735	200	0	0	25	0	0	0	0	26720	17	4	19	52	25	80100	100	80000	100	80000	500	1177584	0	49	23636	26735	26735	16658	3	16693	80100	200	80000	200	80000	26735	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	59	80055	0	0	25	80055	0	0	55	44	5110	4	16	3	1	26712	0	10	10	6	80000	100	26744	26736	26745	26736	26717
80204	26735	200	0	0	61	0	0	0	1	26720	17	4	19	20	25	80100	100	80000	100	80000	500	1177584	0	49	23635	26735	26735	16658	3	16693	80100	200	80000	200	80000	26736	65	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80055	5	0	58	80025	6	1	25	44	5110	3	16	4	1	26732	0	10	0	4	80000	100	26736	26736	26716	26737	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	0	0	1	0	0	0	0	1	26716	2	0	12	16	25	80010	10	80000	10	80000	50	1166896	1	49	23647	26728	26708	16652	3	16717	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	39	80039	6	1	39	43	0	0	5020	4	16	0	3	3	26731	10	10	0	80000	10	26728	26728	26728	26728	26728
80024	26708	200	0	0	0	0	0	45	1	0	26693	0	1	12	19	25	80010	10	80000	10	80000	50	1166886	1	49	23647	26731	26731	16672	3	16688	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	0	80039	6	1	19	43	0	0	5020	2	16	0	3	2	26724	14	10	0	80000	10	26728	26728	26728	26737	26728
80024	26728	200	0	0	0	0	0	0	1	1	26716	0	0	1	1	25	80010	10	80000	10	80000	50	1167124	1	49	23628	26728	26708	16652	3	16711	80010	20	80000	20	80771	26734	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	43	80039	0	0	0	39	80039	6	0	39	44	0	0	5020	3	16	0	3	3	26728	0	10	7	80000	10	26757	26900	26893	26729	26729
80024	26731	200	0	0	0	0	0	45	1	0	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1166896	1	49	23647	26727	26728	16652	3	16708	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80000	0	0	0	39	80039	6	0	39	43	0	0	5020	3	16	0	3	3	26725	10	10	4	80000	10	26732	26709	26709	26709	26732
80024	26728	200	0	0	0	0	0	44	0	1	26716	0	12	12	19	25	80010	10	80000	10	80000	50	1167124	1	49	23651	26728	26708	16676	3	16708	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	39	80039	6	1	39	44	0	0	5020	2	16	0	2	3	26725	13	10	4	80000	10	26709	26729	26709	26729	26728
80024	26708	200	0	0	0	0	0	0	1	1	26712	3	12	12	16	25	80010	10	80000	10	80000	50	1167124	1	49	23651	26731	26731	16672	3	16688	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80000	0	0	0	39	80039	6	1	39	43	0	0	5020	3	16	0	3	3	26725	10	0	0	80000	10	26738	26738	26738	26737	26716
80024	26728	200	0	0	0	0	0	67	1	1	26712	2	12	0	0	25	80010	10	80000	10	80000	50	1168843	1	49	23628	26731	26727	16672	3	16708	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80039	0	1	0	0	80039	6	1	19	43	19	0	5020	3	16	0	3	3	26705	10	10	4	80000	10	26716	26716	26709	26709	26737
80024	26715	200	1	0	0	0	0	45	0	1	26712	0	12	12	0	25	80010	10	80000	10	80000	50	1166750	1	49	23628	26728	26728	16672	3	16707	80010	20	80000	20	80000	26738	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80000	0	0	0	0	80000	6	1	39	43	0	0	5020	3	16	0	3	3	26705	0	0	4	80000	10	26728	26730	26709	26734	26729
80024	26728	200	0	0	0	0	0	45	1	1	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23647	26727	26727	16652	3	16716	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	44	80039	0	0	0	39	80038	6	1	39	43	0	0	5020	3	16	0	3	2	26724	13	13	5	80000	10	26732	26732	26738	26738	26715
80024	26727	200	0	0	0	0	0	0	1	1	26712	0	12	0	0	25	80010	10	80000	10	80000	50	1166750	1	49	23648	26708	26708	16672	3	16708	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	42	80040	6	1	39	44	0	0	5020	4	16	0	3	3	26728	14	14	7	80000	10	26729	26709	26732	26732	26732

LDRSB (unsigned offset, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations