Firestorm: CBNZ (not taken) measurements

Code:

  cbnz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3120	18	2	2	0	0	50	25	1000	1000	1000	5000	0	2056	1942	3	18	1000	1000	1000	1962	1890	1	1	1001	1000	1000	0	0	1932	659	1036	464	417	1971	1847	1989	1983	2085	1965
1004	2074	15	1	1	0	0	62	25	1000	1000	1000	5000	1	1988	1976	3	18	1000	1000	1000	2060	1950	1	1	1001	1000	1000	0	0	1958	473	992	496	449	1967	1959	1977	1925	2069	2081
1004	1902	15	0	1	0	0	35	25	1000	1000	1000	5000	1	1986	1966	3	18	1000	1000	1000	2042	1996	1	1	1001	1000	1000	0	0	1948	517	940	478	418	1941	2015	1907	1995	1977	2015
1004	2146	15	0	0	0	0	33	25	1000	1000	1000	5000	1	1992	1972	3	18	1000	1000	1000	1966	1864	1	1	1001	1000	1000	0	12	1980	471	822	431	525	1861	2059	1987	1845	2017	1993
1004	2104	14	0	1	0	0	41	25	1000	1000	1000	5000	1	2038	1980	3	18	1000	1000	1000	1958	2100	1	1	1001	1000	1000	0	0	1976	476	960	507	465	2043	2055	1965	1959	2055	2019
1004	2090	15	0	0	0	0	35	25	1000	1000	1000	5000	0	1966	2000	3	18	1000	1000	1000	1976	2116	1	1	1001	1000	1000	0	0	2004	475	816	438	523	1929	2081	1979	1867	2009	2081
1004	1850	15	0	1	0	0	41	25	1000	1000	1000	5000	1	1998	2202	3	18	1000	1000	1000	1958	1926	1	1	1001	1000	1000	2	0	1914	486	954	525	512	1933	2009	1977	1873	2067	2015
1004	2056	14	0	1	0	0	35	25	1000	1000	1000	5000	1	2020	1974	3	18	1000	1000	1000	1960	1930	1	1	1001	1000	1000	0	0	1966	430	1004	501	484	2153	1965	2095	1999	1999	1949
1004	1914	14	0	0	0	0	35	25	1000	1000	1000	5000	1	1976	1882	3	18	1000	1000	1000	1968	1994	1	1	1001	1000	1000	6	3	2022	458	988	475	476	1913	1959	2071	1959	2043	1949
1004	2004	15	0	0	0	0	41	25	1000	1000	1000	5000	1	1874	2174	3	18	1000	1000	1000	1962	1964	1	1	1001	1000	1000	0	3	1884	504	916	443	458	1893	1959	1971	1901	2011	1993

Count: 8

Code:

  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	40450	303	0	693	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	301	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	475	1	1	1	5171	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40423	40091	40091
80204	40090	300	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	28	28	80110	80110	80114	400560	1	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	693	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	301	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	42871	309	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80884	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	5	20	3	5	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	3	20	5	5	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	625	25	80010	80010	80010	400050	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	5	20	5	3	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	5	20	5	3	40037	0	10	40041	40041	40041	40041	40041
80024	40040	299	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	6	20	5	3	40037	0	10	40041	40041	40041	40041	42350
80024	40040	300	42	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	5	20	5	3	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	1	0	0	0	0	5020	5	20	6	4	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	4	20	5	5	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	53	0	0	0	0	5020	5	20	5	5	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	5020	5	20	5	5	40037	0	10	40041	40041	40041	40041	40041

CBNZ (not taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations