Firestorm: STRH (unsigned offset) measurements

Code:

  strh w0, [x6, #8]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	563	4	1	1	0	0	18	0	1	537	16	16	0	25	1000	1000	1000	22693	1	552	554	365	3	410	1000	1000	2000	563	554	1	1	1001	1000	1000	1015	15	44	0	1	1014	0	2	14	1002	16	44	14	0	73	1	16	1	1	539	1000	541	543	543	543	541
1004	540	4	0	0	0	0	14	0	1	532	0	16	4	25	1000	1000	1000	22692	1	551	554	366	3	405	1000	1000	2000	547	554	1	1	1001	1000	1000	1015	14	0	0	0	1014	0	1	17	1002	16	44	14	2	73	1	16	1	1	551	1000	555	555	555	555	554
1004	552	4	1	1	1	0	17	0	1	532	16	16	2	25	1000	1000	1000	22692	1	554	552	360	3	405	1000	1000	2000	554	547	1	1	1001	1000	1000	1015	15	44	0	2	1014	0	1	18	1002	16	0	14	0	73	1	16	1	1	551	1000	555	555	555	554	553
1004	552	4	1	0	0	6	14	0	1	532	0	16	1	25	1000	1000	1000	23028	1	547	553	376	3	410	1000	1000	2000	563	554	1	1	1001	1000	1000	1014	15	44	1	1	1016	0	2	17	1002	14	44	14	0	73	1	16	1	1	552	1000	553	549	555	548	555
1004	554	4	1	1	0	6	14	0	1	539	16	0	1	25	1000	1000	1000	23028	1	554	548	367	3	421	1000	1000	2000	554	552	1	1	1001	1000	1000	1014	15	44	0	0	1016	0	1	16	1002	16	44	14	0	73	1	16	1	1	544	1000	548	555	548	548	555
1004	553	4	1	0	0	0	20	0	1	539	0	15	1	25	1000	1000	1000	22692	1	554	552	360	3	410	1000	1000	2000	554	553	1	1	1001	1000	1000	1014	14	44	0	1	1016	0	1	18	1002	14	42	14	1	73	1	16	1	1	551	1000	555	555	555	555	555
1004	547	4	1	0	0	0	15	1	1	539	16	0	2	25	1000	1000	1000	23028	1	547	563	367	3	422	1000	1000	2000	547	547	1	1	1001	1000	1000	1015	15	44	0	0	1016	0	0	17	1002	16	0	14	1	73	1	16	1	1	548	1000	555	555	553	552	548
1004	563	4	1	0	1	0	14	1	1	539	16	16	7	25	1000	1000	1000	22693	1	554	547	367	3	412	1000	1000	2000	554	552	1	1	1001	1000	1000	1015	15	0	0	0	1016	0	2	14	1002	16	44	14	1	73	1	16	1	1	545	1000	548	553	553	656	555
1004	554	4	1	0	1	0	20	1	1	539	16	0	2	25	1000	1000	1000	23028	1	547	563	367	3	421	1000	1000	2000	554	547	1	1	1001	1000	1000	1016	15	0	0	1	1016	0	0	18	1000	16	44	14	0	73	1	16	1	1	549	1000	555	548	553	553	549
1004	564	4	1	1	0	12	14	0	1	537	0	16	1	25	1000	1000	1000	22908	1	551	554	366	3	405	1000	1000	2000	553	547	1	1	1001	1000	1000	1014	15	44	0	1	1016	0	0	19	1002	16	44	14	1	73	1	16	1	1	561	1000	554	553	553	565	555

Count: 8

Code:

  strh w0, [x6, #8]
  strh w0, [x6, #8]
  strh w0, [x6, #8]
  strh w0, [x6, #8]
  strh w0, [x6, #8]
  strh w0, [x6, #8]
  strh w0, [x6, #8]
  strh w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	1	0	1	0	0	18	0	0	1	40032	16	0	4	25	80100	100	80000	100	80000	500	1840220	0	49	36967	40049	40052	29965	3	30010	80100	200	80000	200	160000	40047	32003	1	1	80201	100	99	100	80000	100	80000	100	80016	14	36	0	0	80014	0	0	19	80000	16	36	14	0	5110	1	16	1	1	40055	80000	100	40059	40048	40060	40048	40053
80204	40060	300	1	0	1	0	0	18	1	0	1	40043	16	16	5	25	80100	100	80000	100	80000	500	1839788	0	49	36979	40052	40059	29960	3	30017	80100	200	80000	200	160000	40059	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	14	36	0	1	80016	0	0	17	80000	14	36	14	1	5110	1	16	1	1	40044	80000	100	40059	40050	40048	40048	40053
80204	40060	299	1	0	0	0	0	19	0	0	1	40043	0	16	5	25	80100	100	80000	100	80000	500	1839932	0	49	36980	40047	40058	29970	3	30005	80100	200	80144	200	160000	40061	32000	1	1	80201	100	99	100	80000	100	80000	100	80015	14	0	0	0	80016	0	0	18	80002	16	36	14	1	5110	1	16	1	3	40179	80000	100	40061	40048	40050	40048	40060
80204	40059	300	1	0	1	0	0	19	0	0	1	40032	0	16	2	25	80100	100	80000	100	80000	500	1839860	1	49	36972	40061	40051	29960	3	30010	80100	200	80000	200	160000	40060	39647	1	1	80201	100	99	100	80000	100	80000	100	80014	14	36	1	1	80016	0	1	14	80002	16	36	14	1	5110	1	16	1	1	40047	80000	100	40062	40048	40061	40060	40059
80204	40052	300	1	1	0	0	0	14	1	0	1	40032	16	16	0	25	80100	100	80000	100	80000	500	1840341	1	49	36970	40059	40061	29972	3	30010	80100	200	80000	200	160000	40059	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	14	0	0	2	80016	0	1	18	80000	16	36	14	2	5110	1	16	1	1	40049	80000	100	40051	40060	40052	40059	40062
80204	40058	300	1	0	1	0	0	19	0	0	1	40032	0	16	5	25	80100	100	80000	100	80000	500	1839884	0	49	36979	40059	40059	29960	3	30018	80100	200	80000	200	160000	40047	32012	1	1	80201	100	99	100	80000	100	80000	100	80014	14	36	0	0	80016	0	2	17	80002	16	0	14	0	5110	1	16	1	1	40045	80000	100	40060	40048	40059	40053	40059
80204	40047	300	1	0	1	0	0	18	0	0	1	40032	16	16	5	25	80100	100	80000	100	80000	500	1839932	1	49	36967	40051	40047	29960	3	30017	80100	200	80000	200	160000	40052	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	14	36	0	0	80016	0	2	20	80000	16	36	14	2	5110	1	16	0	1	40054	80000	100	40059	40048	40048	40053	40048
80204	40050	300	1	1	0	0	0	21	0	0	1	40032	16	16	5	25	80100	100	80000	100	80000	500	1839692	1	49	36978	40047	40052	29965	3	30016	80100	200	80000	200	160000	40053	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	16	36	0	1	80014	0	0	20	80002	16	36	14	0	5110	1	16	1	1	40044	80000	100	40059	40053	40060	40054	40060
80204	40051	300	1	0	1	0	12	19	1	0	1	40032	0	16	9	25	80100	100	80000	100	80000	500	1839719	0	49	36972	40047	40053	29965	3	30019	80100	200	80000	200	160000	40188	32000	1	1	80201	100	99	100	80000	100	80000	100	80015	15	36	0	2	80016	0	3	20	80060	16	0	14	1	5110	1	16	1	1	40044	80000	100	40049	40053	40062	40053	40060
80204	40053	300	1	0	1	2	306	17	1	0	1	40032	16	16	2	25	80100	100	80000	100	80000	500	1839692	0	49	36967	40047	40047	29972	3	30017	80100	200	80000	200	160000	40052	32011	1	1	80201	100	99	100	80000	100	80000	100	80014	15	36	0	0	80016	0	0	18	80000	16	36	14	0	5110	1	16	1	1	40047	80000	100	40060	40048	40062	40048	40060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40043	300	0	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	0	49	36963	40040	40040	29975	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	2	80002	2	42	0	5020	9	16	0	0	4	9	9	40039	80000	10	40055	40041	40044	40043	40044
80024	40042	300	0	0	3	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	0	49	36962	40054	40042	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	2	80002	0	42	0	5020	8	16	0	0	3	9	9	40039	80000	10	40041	40043	40041	40041	40044
80024	40043	300	0	0	3	0	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839352	0	0	49	36960	40040	40042	29978	3	30020	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80002	0	5	80000	2	42	0	5020	8	16	0	0	1	9	9	40040	80000	10	40044	40043	40041	40044	40043
80024	40040	300	0	6	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	1	49	36960	40042	40040	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	2	80002	2	0	0	5020	11	16	0	0	2	10	10	40039	80000	10	40044	40044	40041	40043	40044
80024	40040	300	0	0	3	1	0	40039	0	16	0	25	80010	10	80000	10	80000	50	1839472	0	0	49	36962	40042	40042	29975	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80000	0	2	80002	2	0	0	5020	10	16	0	0	1	11	9	40037	80000	10	40043	40043	40043	40043	40043
80024	40042	300	0	0	3	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839448	0	0	49	36960	40040	40042	29977	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80060	42	80000	1	2	80002	2	42	0	5020	10	16	0	0	1	10	9	40039	80000	10	40043	40043	40041	40043	40041
80024	40042	300	0	0	3	1	0	40025	16	16	1	25	80010	10	80000	10	80000	50	1839905	0	0	49	36974	40040	40040	29977	3	30020	80010	20	80000	20	160000	40043	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80000	0	2	80002	2	0	0	5020	9	16	0	0	1	9	10	40039	80000	10	40043	40041	40043	40043	40041
80024	40042	300	0	0	15	1	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839352	0	0	49	36962	40040	40042	29978	3	30022	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80000	0	2	80002	2	0	0	5020	9	16	0	0	1	10	9	40039	80000	10	40044	40043	40041	40044	40043
80024	40043	299	0	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	0	49	36960	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80002	0	0	80000	2	42	0	5020	11	16	0	0	0	9	12	40037	80000	10	40041	40041	40043	40041	40041
80024	40040	300	0	0	3	0	0	40025	16	0	1	25	80010	10	80000	10	80000	50	1839352	0	0	49	36963	40043	40043	29975	3	30020	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80000	0	2	80002	2	42	0	5020	8	16	0	0	0	9	8	40040	80000	10	40043	40044	40041	40043	40043

STRH (unsigned offset)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations