Firestorm: BICS (register, lsl, 64-bit) measurements

Code:

  bics x0, x0, x1, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	84	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	21	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1741	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	76	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1088	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	169	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	14	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  bics x0, x0, x1, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	84	10000	19868	47	20100	20100	10105	1305150	0	49	16955	20035	20035	18608	8	18735	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	0	16	0	0	19954	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	61	10000	19868	25	20100	20100	10105	1305150	0	49	16955	20035	20035	18608	8	18735	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	3	0	1	1	1	720	0	16	0	0	19954	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	82	10000	19868	25	20100	20100	10105	1305150	1	49	16955	20035	20035	18608	8	18736	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	3	0	1	1	1	720	0	16	0	0	19954	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	61	10000	19868	25	20100	20100	10105	1305150	0	49	16955	20035	20035	18608	8	18736	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	3	0	1	1	1	720	0	16	0	0	19954	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	61	10000	19868	25	20100	20100	10105	1305150	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	45	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	3	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	50	6	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	3	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	149	0	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	5	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	151	0	0	61	10000	19870	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	15	0	145	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20071	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	417	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	21	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  bics x0, x1, x0, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	84	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	3	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	2	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	84	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	2	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19868	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	1	0	3	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10022	10	9	10	10010	10	0	0	6	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20071	41	1	1	10021	10	9	10	10010	10	0	0	3	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	4	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	41	0	9	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	103	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	2	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  bics x0, x1, x2, lsl #17
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	61	10000	29899	30019	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	0	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	16	0	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	0	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	2	2	0	1	1	1	1320	16	0	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	61	10000	29899	0	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	0	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	0	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	3	0	0	1	1	1	1319	16	2	1	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	61	10000	29899	0	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	0	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	0	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	1	2	0	1	1	1	1319	16	0	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	0	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	0	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	3	0	3	1	1	1	1319	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	3	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	3	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	0	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	3	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	2	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	0	2	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	2	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	2317	0	1270	2	1	33	2	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	1	0	0	1	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	2	49	27320	0	30353	30355	27483	38	27656	20620	20640	31090	30396	85	9	1	20021	10	9	10	20010	10010	0	0	0	1	2	7768	0	1382	2	3	104	1	1	30195	30176	20010	30356	30355	30402	30400	30263
20024	30401	227	1	0	1	7	8	1068	662	1	2064	10048	29919	194	30166	30164	20623	1962112	0	2	49	27274	0	30348	30400	27473	44	27684	20543	20734	31052	30353	85	8	1	20021	10	9	10	20010	10010	6	2	0	1	0	3030	4	1433	2	1	105	1	4	30265	30220	20010	30494	30493	30449	30488	30488
20024	30445	228	0	1	0	10	11	1452	794	0	2468	10060	29927	236	30230	30208	20774	1962853	1	0	49	27409	0	30528	30489	27461	48	27762	20315	20906	31339	30491	85	10	1	20021	10	9	10	20010	10010	0	0	0	1	4	10630	0	1430	0	3	113	3	2	30296	30221	20010	30492	30490	30533	30492	30537
20024	30447	228	0	1	0	11	11	1323	880	0	3177	10060	29921	240	30211	30208	20618	1963552	0	2	49	27364	0	30491	30171	27506	52	27629	20777	20198	30956	30311	85	9	1	20021	10	9	10	20010	10010	0	3	0	0	4	4113	2	1388	0	2	81	3	2	30024	30154	20010	30264	30265	30354	30172	30302
20024	30173	227	0	1	0	5	4	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	2	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	1	1	0	0	0	1270	2	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	2	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	0	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  bics x0, x1, x2, lsl #17
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29989	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29988	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29988	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29988	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	29989	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	29988	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29988	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	29988	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	3	1	1	1	1320	1	16	1	1	29989	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	1	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	29989	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	0	0	0	0	0	0	0	124	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	1	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	149	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	1	33	2	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	51	0	0	453	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	3	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	6	92	3	2	30212	30044	20010	30307	30356	30355	30401	30355
20024	30391	227	1	1	1	7	7	933	616	1	2850	10042	29903	169	30186	30166	20544	1961387	0	0	49	27273	30398	30174	27483	39	27707	20544	20642	31085	30353	85	6	1	20021	10	9	10	20010	10010	2	0	0	1	2	7158	2	1302	3	92	3	1	30226	30176	20010	30354	30399	30400	30355	30354
20024	30354	227	0	1	1	7	8	936	704	0	3293	10030	29919	69	30188	30186	20544	1962114	0	0	49	27273	30397	30355	27460	33	27679	20546	20647	31089	30403	85	8	1	20021	10	9	10	20010	10010	0	4	0	1	0	8255	2	1318	1	87	3	1	30231	30154	20010	30355	30403	30355	30399	30354
20024	30403	227	1	0	0	8	3	1056	616	0	2333	10048	29899	197	30186	30188	20544	1961398	0	0	49	27275	30312	30354	27470	39	27707	20621	20731	31084	30401	85	9	1	20021	10	9	10	20010	10010	4	2	2	1	2	7080	2	1436	6	113	3	1	30163	30176	20010	30444	30483	30446	30446	30490
20024	30309	227	0	1	1	10	10	1197	792	0	2996	10060	29927	216	30208	30231	20395	1962814	0	1	49	27273	30218	30356	27436	34	27683	20548	20641	30952	30216	85	4	1	20021	10	9	10	20010	10010	0	2	0	0	0	7050	4	1304	1	60	2	3	30195	30154	20010	30262	30262	30126	30036	30036
20024	30035	224	0	0	0	0	0	0	0	0	84	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	1	0	9	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036

Test 6: throughput

Count: 8

Code:

  bics x0, x8, x9, lsl #17
  bics x1, x8, x9, lsl #17
  bics x2, x8, x9, lsl #17
  bics x3, x8, x9, lsl #17
  bics x4, x8, x9, lsl #17
  bics x5, x8, x9, lsl #17
  bics x6, x8, x9, lsl #17
  bics x7, x8, x9, lsl #17

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	53447	400	0	0	0	0	875	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53458	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	166	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	650	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	170	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	145	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	214	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43384	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	1	0	0	191	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	103	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	149	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53461	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	191	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	53401	399	0	0	0	0	500	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	0	21	24	0	15	15	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	147	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	4	0	5020	0	1	1	13	24	0	13	15	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	177	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	0	0	17	24	0	16	14	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	149	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5022	0	0	0	14	24	0	11	10	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	191	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	0	16	24	0	14	9	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	191	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	0	10	24	0	17	14	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	170	80000	47946	25	160010	160010	80010	3438130	0	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	0	15	24	0	13	12	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	212	80000	47946	25	160010	160010	80010	3440708	0	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	0	17	24	0	14	10	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	403	80000	47946	25	160010	160010	80010	3438130	0	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	0	16	24	0	12	16	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	197	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	0	13	24	0	13	11	53360	160000	0	80010	53381	53381	53381	53381	53381

BICS (register, lsl, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations