Firestorm: DMB (OSHLD) measurements

Code:

  dmb oshld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst barrier (9c)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	3026	23	0	3020	2009	1000	1000	1000	6000	0	34	3027	3035	3	2885	1000	1000	3027	3027	1	1	1001	1000	1000	0	0	73	2	16	1	1	3023	1000	3036	3028	3036	3027	3036
1004	3035	23	0	3011	2001	1000	1000	1000	6000	0	33	3026	3035	3	2893	1000	1000	3035	3035	1	1	1001	1000	1000	0	0	73	1	16	1	1	3032	1000	3028	3036	3027	3036	3027
1004	3026	23	0	3011	2001	1000	1000	1000	6000	0	34	3027	3035	3	2885	1000	1000	3026	3026	1	1	1001	1000	1000	0	0	73	1	16	1	1	3023	1000	3036	3027	3036	3028	3036
1004	3035	22	0	3012	2001	1000	1000	1000	6000	0	33	3027	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	1000	0	0	73	1	16	1	1	3032	1000	3027	3036	3027	3036	3027
1004	3026	23	0	3012	2001	1000	1000	1000	6000	0	34	3027	3035	3	2893	1000	1000	3035	3035	1	1	1001	1000	1000	0	0	73	1	16	1	1	3022	1000	3036	3028	3036	3028	3028
1004	3027	23	0	3020	2000	1000	1000	1000	6000	0	34	3027	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	1000	0	0	73	1	16	1	1	3023	1000	3028	3036	3028	3036	3027
1004	3026	23	0	3171	2001	1000	1000	1000	6000	0	34	3026	3035	3	2893	1000	1000	3035	3035	1	1	1001	1000	1000	0	0	73	1	16	1	1	3024	1000	3036	3027	3036	3027	3036
1004	3035	22	0	3012	2001	1000	1000	1000	6000	0	34	3025	3035	3	2893	1000	1000	3026	3026	1	1	1001	1000	1000	0	0	73	1	16	1	1	3023	1000	3036	3028	3036	3027	3036
1004	3035	22	0	3011	2000	1000	1000	1000	6000	0	34	3026	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	1000	0	0	73	1	16	1	1	3032	1000	3028	3036	3028	3036	3027
1004	3026	23	0	3012	2009	1000	1000	1000	6000	0	42	3035	3027	3	2884	1000	1000	3027	3027	1	1	1001	1000	1000	0	0	73	1	16	1	1	3032	1000	3028	3036	3028	3036	3027

Code:

  dmb oshld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.9044

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	st unit uop (a7)	l1d cache writeback (a8)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	29135	217	0	0	0	0	0	0	0	29020	18917	10100	100	10000	100	10000	500	59800	1	49	25963	29135	29035	3	27843	10100	200	10000	200	29135	23295	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29773	0	10000	100	29136	29035	29136	29026	29136
10204	29135	217	0	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	25954	29135	29025	3	27843	10100	200	10000	200	29135	23295	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29132	0	10000	100	29028	29136	29037	29136	29026
10204	29025	218	0	0	0	0	0	0	0	29028	19480	10178	123	10060	124	10056	610	62856	1	49	26055	29043	29135	3	27843	10100	200	10000	200	29135	23295	1	1	10201	100	99	100	100	10000	100	10055	0	2	893	2	104	2	2	30732	21	10000	100	30503	29617	31049	30863	30537
10204	30512	236	0	1	1	15	14	1332	1320	29120	20237	10123	100	10000	100	10000	500	59800	0	49	25945	29135	29035	3	27750	10100	200	10000	200	29042	23214	1	1	10201	100	99	100	100	10000	100	10000	42	0	710	2	16	2	2	29132	0	10000	100	29036	29136	29136	29036	29136
10204	29135	217	0	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	25963	29135	29043	3	27743	10100	200	10000	200	29035	23216	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29132	0	10000	100	29136	29044	29136	29035	29136
10204	29135	217	0	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	1	49	25955	29135	29027	3	27742	10100	200	10000	200	29035	23295	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29132	0	10000	100	29035	29136	29044	29136	29037
10204	29036	219	0	0	0	0	0	0	0	29020	18906	10100	100	10000	100	10000	500	59800	0	49	26055	29033	29135	3	27843	10100	200	10000	200	29034	23215	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29132	0	10000	100	29036	29136	29029	29136	29036
10204	29035	218	0	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	25963	29135	29043	3	27743	10100	200	10000	200	29035	23295	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29132	0	10000	100	29029	29136	29035	29136	29028
10204	29027	218	0	0	0	0	0	0	0	29010	18916	10100	100	10000	100	10000	500	59800	1	49	26055	29034	29135	3	27843	10100	200	10000	200	29135	23221	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29132	0	10000	100	29028	29136	29037	29136	29136
10204	29043	218	0	0	0	0	0	0	0	29029	18899	10100	100	10000	100	10000	500	59800	0	49	26055	29025	29135	3	27843	10100	200	10000	200	29135	23215	1	1	10201	100	99	100	100	10000	100	10000	0	0	710	2	16	2	2	29132	0	10000	100	29035	29136	29026	29136	29036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.9867

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	31037	233	1	1	1	8	7	1056	704	1	30860	20555	10076	12	10064	12	10064	55	61910	1	49	27917	31142	31151	27	29781	10092	20	10032	20	31025	31094	10	1	10021	10	9	10	10	10000	10	2	10024	2	4	6790	4	756	4	96	3	4	30991	2	10000	10	31190	31184	31266	31147	31112
10024	31030	229	1	0	0	9	9	1197	792	0	31172	20637	10084	12	10064	12	10086	71	62739	1	49	28104	30304	31114	12	29755	10084	20	10024	20	30953	31102	10	1	10021	10	9	10	10	10000	10	2	10092	1	2	7308	0	757	5	40	3	3	31036	2	10000	10	31195	30867	30882	31031	31146
10024	31158	234	0	0	0	5	10	1320	880	0	30229	20023	10076	12	10027	12	10008	60	59982	1	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29951	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	0	640	2	16	2	3	29864	0	10000	10	29867	29952	29868	29952	29868
10024	29867	224	0	0	0	0	0	0	0	0	29851	19830	10010	10	10000	10	10000	50	59982	1	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29951	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	0	640	3	16	3	3	29862	0	10000	10	29952	29867	29952	29868	29866
10024	29865	225	0	0	0	0	0	0	0	0	29852	19831	10010	10	10000	10	10000	50	59982	1	49	26871	29866	29951	3	28681	10010	20	10000	20	29951	29866	1	1	10021	10	9	10	10	10000	10	0	10000	3	0	0	0	640	2	16	2	3	29948	0	10000	10	29866	29952	29865	29952	29868
10024	29867	225	0	0	0	0	0	0	0	0	29936	19915	10010	10	10000	10	10000	50	59982	1	49	26784	29951	29866	3	28596	10010	20	10000	20	29951	29951	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	0	640	3	16	3	3	29948	0	10000	10	29868	29952	29868	29952	29866
10024	29865	224	0	0	0	0	0	0	0	0	29851	19829	10010	10	10000	10	10000	50	59982	1	49	26871	29866	29951	3	28681	10010	20	10000	20	29951	29865	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	0	640	3	16	2	2	29948	0	10000	10	29868	29952	29868	29952	29866
10024	29865	224	0	0	0	0	0	0	0	0	29936	19915	10010	10	10000	10	10000	50	59982	1	49	26871	29866	29951	3	28681	10010	20	10000	20	29951	29951	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	0	640	2	16	3	3	29948	0	10000	10	29868	29952	29868	29952	29867
10024	29951	223	0	0	0	0	0	0	0	0	29852	19831	10010	10	10000	10	10000	50	59982	1	49	26871	29866	29951	3	28681	10010	20	10000	20	29951	29865	1	1	10021	10	9	10	10	10000	10	0	10000	0	2	0	0	640	2	16	2	2	29948	0	10000	10	29868	29952	29868	29952	29867
10024	29866	224	0	0	0	0	0	0	0	0	29936	19831	10010	10	10000	10	10000	50	59982	1	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	0	640	2	16	3	3	29948	0	10000	10	29867	29952	29867	29952	29868

DMB (OSHLD)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations