Firestorm: LDPSW (post-index) measurements

Code:

  ldpsw x0, x1, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
3005	1040	8	0	0	1	0	0	79	0	0	4	0	1029	15	4	8	5	9	25	2000	1000	1000	1000	1000	52849	45595	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1044	38	1	1	1001	1000	1000	0	1007	8	0	78	1051	2	0	14	0	27	1046	57	6	28	40	7	1	0	73	2	16	2	2	1037	1000	30	25	0	1000	2000	1041	1041	1041	1041	1041
3004	1046	8	1	0	0	0	0	98	12	1	5	8	1029	7	3	6	4	18	25	2000	1000	1000	1000	1000	52818	45589	0	1040	1044	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1030	6	0	53	1045	4	0	30	18	46	1052	33	7	44	64	7	0	0	73	2	16	2	2	1037	1000	37	24	8	1000	2000	1045	1045	1041	1041	1041
3004	1040	7	1	1	0	1	0	61	20	0	3	0	1025	16	2	9	5	20	25	2000	1000	1000	1000	1000	52854	45591	1	1041	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1034	6	2	66	1045	9	1	19	0	40	1029	26	4	28	48	6	1	0	73	2	16	2	2	1037	1000	15	22	0	1000	2000	1041	1045	1041	1045	1041
3004	1040	7	1	1	0	1	0	55	0	0	3	0	1025	0	5	3	6	14	25	2000	1000	1000	1000	1000	52846	45591	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1041	38	1	1	1001	1000	1000	0	1007	7	0	45	1031	0	1	2	0	34	1027	20	4	23	64	7	2	0	73	2	16	2	2	1037	1000	33	22	0	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	1	2	0	0	0	47	0	1	5	0	1025	11	2	18	14	14	25	2000	1000	1000	1000	1000	52845	45591	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1020	6	0	53	1038	0	0	1	0	33	1038	21	4	43	40	7	0	0	73	2	16	2	2	1020	1000	23	20	0	1000	2000	1045	1041	1041	1041	1041
3004	1040	7	1	0	0	1	0	68	18	0	6	12	1025	0	6	11	9	24	25	2000	1000	1000	1000	1000	52837	45589	1	1044	1044	574	3	652	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1008	7	0	71	1049	6	0	28	0	38	1027	17	3	35	48	7	0	0	73	2	16	2	2	1020	1000	35	30	0	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	1	0	1	0	65	14	0	4	0	1029	18	4	12	7	12	25	2000	1000	1000	1000	1000	52857	45590	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1044	38	1	1	1001	1000	1000	0	1023	6	0	33	1044	3	0	19	0	27	1016	28	3	29	48	7	1	0	73	2	16	2	2	1037	1000	24	25	0	1000	2000	1041	1041	1041	1041	1045
3004	1040	7	1	0	0	1	0	82	22	0	2	0	1026	0	2	7	7	10	25	2000	1000	1000	1000	1000	52833	45591	1	1040	1044	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1021	7	1	40	1020	1	0	14	8	16	1022	28	6	16	56	6	1	0	73	2	16	2	2	1037	1000	38	25	0	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	1	1	0	0	0	74	14	1	4	0	1025	10	1	10	9	11	25	2000	1000	1000	1000	1000	52827	45592	1	1044	1040	574	3	652	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1026	8	1	32	1036	1	0	13	12	20	1012	34	3	16	72	7	0	0	73	2	16	2	2	1020	1000	26	22	0	1000	2000	1045	1045	1045	1045	1045
3004	1040	7	1	1	0	0	0	54	14	1	3	0	1025	13	2	4	4	13	25	2000	1000	1000	1000	1000	52849	45590	1	1044	1040	574	3	648	2000	1000	2000	1000	1000	1044	38	1	1	1001	1000	1000	0	1008	7	0	48	1028	0	0	0	0	25	1014	34	3	17	56	6	1	0	73	2	16	2	2	1020	1000	38	24	0	1000	2000	1041	1041	1041	1045	1041

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldpsw x0, x1, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1766

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	0e	0f	1e	20	22	29	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	72189	539	1	0	0	0	537	810	1	608	100	71860	784	4	2	71612	25	50790	40596	10130	40100	10000	618806	2746486	0	49	68533	0	71614	71777	64027	0	3	63997	50301	40200	20000	70200	10000	71608	35	1	1	40201	100	99	100	10000	30100	10000	100	10906	0	135	540	10625	247	12	884	44	26	10901	116	2	137	0	0	9	2610	2	58	1	1	71495	40484	952	918	880	10000	50100	71842	71776	71855	72005	71862
60204	71732	538	0	1	0	1	569	834	1	696	112	71770	787	2	2	71438	25	50730	40640	10128	40100	10000	617852	2738677	1	49	68552	0	71731	71688	63909	0	3	64244	50100	40200	20000	70200	10000	71510	35	1	1	40201	100	99	100	10000	30100	10000	100	10916	0	157	499	10651	238	9	915	48	29	10921	129	2	125	0	5	7	2610	1	58	1	1	71547	40476	946	964	998	10000	50100	71776	71747	71582	71520	72029
60204	71819	539	0	1	0	0	524	831	1	736	124	71699	809	2	3	71656	25	50720	40596	10133	40100	10000	618941	2740848	0	49	68716	0	71722	71875	63960	0	3	64098	50100	40200	20000	70200	10000	71736	35	1	1	40201	100	99	100	10000	30100	10000	100	10926	0	159	492	10653	284	13	940	122	26	10928	131	3	142	0	0	7	2610	1	58	1	1	71495	40476	870	934	866	10000	50100	71954	71645	71907	71773	71548
60204	71829	538	0	0	0	0	589	816	1	720	92	71754	807	2	1	71407	25	50750	40560	10134	40100	10000	618347	2741745	1	49	68521	0	71607	71704	63822	0	3	64382	50100	40200	20000	70200	10000	71894	35	1	1	40201	100	99	100	10000	30100	10000	100	10930	0	149	508	10612	271	10	912	50	35	10937	118	2	141	0	3	5	2673	1	58	1	1	71529	40508	827	904	882	10000	50100	71625	71617	71975	71740	71814
60204	71804	536	0	0	0	0	557	832	1	616	144	71766	835	3	2	71643	25	50725	40560	10122	40100	10000	618896	2739264	1	49	68661	0	71830	72004	63938	0	3	64575	50100	40200	20000	70200	10000	71710	35	1	1	40201	100	99	100	10000	30100	10000	100	10899	0	156	508	10650	261	9	909	78	23	10934	135	2	117	0	3	10	2610	1	58	1	1	71500	40552	1004	952	904	10000	50100	71804	71637	71709	71683	71828
60204	71808	534	0	0	0	0	588	822	1	776	144	71752	777	3	2	71434	25	50765	40664	10139	40100	10000	617231	2738192	1	49	68754	0	71825	71593	64119	0	3	64165	50100	40200	20000	70200	10000	71734	35	1	1	40201	100	99	100	10000	30100	10000	100	10926	1	157	506	10656	267	12	904	32	34	10912	128	2	123	0	0	3	2610	1	58	1	1	71471	40548	940	854	800	10000	50100	71711	71697	71720	71925	71725
60204	71748	537	0	0	0	0	488	815	1	688	132	71651	790	2	3	71577	25	50750	40656	10118	40100	10000	616232	2736618	0	49	68584	0	71752	71616	63943	0	3	64344	50100	40200	20000	70200	10000	71569	35	1	1	40201	100	99	100	10000	30100	10000	100	10904	0	160	504	10651	270	7	912	48	35	10917	119	2	135	0	0	3	2610	1	58	1	1	71717	40528	956	890	864	10000	50100	71881	71695	71917	71720	71835
60204	71870	538	0	0	0	0	617	832	1	704	100	71714	787	2	2	71401	25	50720	40596	10131	40100	10000	619346	2739478	1	49	68467	0	71643	71725	63890	0	3	64121	50100	40200	20000	70200	10000	71877	35	1	1	40201	100	99	100	10000	30100	10000	100	10898	0	113	485	10640	274	6	904	28	30	10921	128	2	127	0	0	3	2610	1	58	1	1	71522	40472	810	862	962	10000	50100	71695	71738	71743	71837	71609
60204	71724	537	0	0	1	0	564	826	1	720	136	71645	800	2	2	71598	25	50770	40600	10130	40100	10000	617366	2745359	0	49	68749	0	71866	71855	64062	0	3	64277	50100	40200	20000	70200	10000	71732	35	1	1	40201	100	99	100	10000	30100	10000	100	10906	0	143	559	10633	264	7	902	80	32	10913	132	2	133	0	3	9	2610	1	58	1	1	71779	40532	830	894	940	10000	50100	71874	71704	71766	71897	71757
60204	71717	538	0	2	0	0	494	820	1	704	104	71825	796	3	2	71677	25	50805	40660	10143	40100	10000	617591	2747003	1	49	68839	0	71710	71727	63987	0	3	64134	50100	40200	20000	70200	10000	71633	35	1	1	40201	100	99	100	10000	30100	10000	100	10928	0	139	497	10654	253	10	937	34	26	10940	140	2	132	0	0	9	2610	1	58	1	1	71542	40508	1026	922	920	10000	50100	71685	71733	71982	71846	71758

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1986

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	72268	538	0	1	0	614	0	839	1	736	0	116	72008	812	6	2	72017	25	50755	40566	10143	40010	10000	619795	2746972	0	0	49	68970	72062	72407	64203	0	3	64682	50010	40020	20000	70020	10000	72110	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10936	151	480	10661	284	11	944	50	34	10938	127	7	129	3	8	2520	0	3	64	0	0	0	2	2	71711	40576	1064	1049	952	10000	50010	72082	72012	72007	71983	72072
60024	71903	540	0	0	0	463	0	790	1	704	0	132	71896	800	6	2	71741	25	50720	40634	10130	40010	10000	622860	2761061	0	0	49	68944	71966	72113	64210	0	3	64378	50010	40020	20000	70020	10000	71981	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10921	172	480	10651	261	51	948	54	33	10929	126	6	124	0	0	2520	0	2	64	0	0	0	2	2	71795	40552	1115	1108	1101	10000	50010	71921	72057	72037	71921	71946
60024	72109	540	0	0	0	958	0	831	1	736	0	100	72057	809	4	1	71709	25	50655	40550	10128	40010	10000	619597	2752419	0	1	49	68797	71859	72005	64286	0	3	64464	50010	40020	20000	70020	10000	71957	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10917	160	507	10653	282	15	877	22	37	10941	139	7	133	0	2	2520	0	2	64	0	0	0	2	2	71919	40548	1116	1019	1118	10000	50010	71984	72134	71985	71864	71799
60024	71964	539	0	0	0	485	0	846	1	736	0	108	71903	785	6	2	71741	25	50700	40514	10141	40010	10000	617590	2745193	0	1	49	68958	71953	72000	64016	0	3	64131	50010	40020	20000	70020	10000	72012	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10914	135	491	10639	276	11	902	28	46	10886	129	11	126	3	0	2520	0	2	64	0	0	0	2	2	71734	40564	1054	1027	1169	10000	50010	72058	71949	72069	72087	71878
60024	72026	538	0	0	0	463	0	826	1	704	0	108	71938	819	4	2	71784	25	50740	40550	10153	40010	10000	618670	2754221	1	1	49	68945	71923	71839	64045	0	3	64432	50010	40020	20000	70020	10000	71947	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10921	147	473	10642	267	14	899	80	31	10884	122	6	132	3	1	2520	0	2	64	0	0	0	2	2	71655	40576	1014	1144	1113	10000	50010	72026	72069	72015	71904	71944
60024	71937	539	0	0	0	464	0	821	1	712	0	108	71716	790	6	2	71736	25	50685	40518	10127	40010	10000	617950	2759290	0	0	49	68839	71841	71792	64249	0	3	64420	50010	40020	20000	70020	10000	71884	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10927	146	511	10621	259	13	902	66	42	10914	125	10	129	0	0	2520	0	2	64	0	0	0	2	2	71815	40552	1162	1106	1108	10000	50010	71903	71895	72012	71907	71993
60024	71756	539	0	0	0	465	0	832	1	744	0	112	71861	803	6	3	71843	25	50700	40522	10128	40010	10000	618796	2744507	0	0	49	68954	71861	71949	64156	0	3	64392	50010	40020	20000	70020	10000	71856	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10910	158	483	10634	273	13	928	54	37	10923	127	6	131	3	11	2520	0	2	64	0	0	0	2	2	71716	40516	1024	1046	1118	10000	50010	71971	72092	72008	72007	72058
60024	71911	539	0	0	0	490	0	836	1	744	1	128	71908	793	7	2	71708	25	50675	40546	10131	40010	10000	619921	2752611	0	0	49	68915	72098	72221	64177	0	3	64247	50010	40020	20000	70020	10000	71988	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10895	177	492	10635	270	9	909	48	28	10917	115	7	124	3	8	2520	0	2	64	0	0	0	2	2	71898	40612	1034	1083	1081	10000	50010	71725	71967	71996	71714	72397
60024	71939	540	0	0	0	459	0	815	1	736	0	140	71906	840	6	2	71851	25	50730	40554	10141	40010	10000	618607	2750973	0	0	49	68870	71943	72242	64173	0	3	64480	50010	40020	20000	70020	10000	71772	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10912	150	503	10665	262	12	926	70	36	10907	136	7	137	0	0	2520	0	2	64	0	0	0	2	2	71804	40564	1085	1111	1088	10000	50010	71898	71958	72014	71976	72007
60024	71986	538	0	0	0	470	0	836	1	720	1	168	72001	831	8	1	71696	25	50700	40526	10141	40010	10000	618724	2754501	0	0	49	68928	71935	72178	64102	0	3	64503	50010	40020	20000	70020	10000	71933	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10916	145	538	10721	262	10	940	58	36	10949	122	7	126	0	0	2520	0	2	64	0	0	0	2	2	71907	40532	1113	1021	1071	10000	50010	71926	72020	72022	71892	71839

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldpsw x0, x1, [x6], #8
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1873

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	72078	542	0	1	365	0	842	1	712	0	80	71861	774	2	2	71717	25	50705	40596	10118	40100	10000	618035	2747595	0	49	68865	0	71761	71739	64119	3	64414	50100	40200	20000	70200	10000	71808	35	1	1	40201	100	99	100	10000	30100	10000	100	10914	157	506	10644	254	9	878	44	14	10896	124	2	122	0	0	0	2610	2	57	1	1	71832	40532	999	1028	1117	10000	50100	71927	72056	71934	72049	71941
60204	71812	539	0	0	424	0	807	1	736	0	140	71871	772	2	2	71734	25	50775	40632	10121	40100	10000	618692	2748458	0	49	68826	0	71874	71794	64093	3	64441	50100	40200	20000	70200	10000	71884	35	1	1	40201	100	99	100	10000	30100	10000	100	10859	166	465	10632	270	9	894	28	11	10931	124	2	130	0	8	0	2610	1	57	1	1	71581	40488	1266	1144	1057	10000	50100	71799	72046	71871	71825	71935
60204	71996	539	0	1	390	0	798	1	776	0	56	71779	796	2	3	71600	25	50670	40552	10122	40100	10000	620393	2743839	1	49	68786	0	71827	72028	64056	3	64252	50100	40200	20000	70200	10000	71831	35	1	1	40201	100	99	100	10000	30100	10000	100	10906	149	484	10609	252	7	897	74	20	10870	124	2	127	0	4	0	2610	1	57	1	1	71743	40532	956	1183	938	10000	50100	71893	71596	71822	71760	71897
60204	71908	539	0	0	457	0	780	1	536	0	88	71695	769	2	2	71665	25	50710	40624	10132	40100	10000	619277	2743425	0	49	68774	0	71865	71762	63937	3	64233	50100	40200	20000	70200	10000	71976	35	1	1	40201	100	99	100	10000	30100	10000	100	10915	175	492	10671	248	7	908	120	20	10923	115	2	126	0	18	0	2610	1	57	1	1	71844	40480	1114	1029	1082	10000	50100	71992	72055	72083	71994	71932
60204	71963	538	0	0	387	0	796	1	688	0	112	71767	805	3	2	71631	25	50735	40648	10122	40100	10000	620330	2747045	0	49	68767	0	71765	71909	64025	3	64300	50100	40200	20000	70200	10000	71852	35	1	1	40201	100	99	100	10000	30100	10000	100	10894	162	506	10637	239	8	908	32	20	10877	123	2	116	3	6	0	2610	1	57	1	1	71568	40508	968	1095	984	10000	50100	71564	71879	71895	71827	72088
60204	71577	538	0	0	329	0	811	1	728	0	132	71666	786	2	3	71514	25	50745	40604	10130	40100	10000	619556	2741711	0	49	68861	3	71656	71914	64051	3	64302	50100	40200	20000	70200	10000	71640	35	1	1	40201	100	99	100	10000	30100	10000	100	10905	154	467	10613	273	6	901	94	14	10905	130	2	139	0	3	0	2610	1	57	1	1	71715	40472	1095	1062	1115	10000	50100	71938	71942	72006	71912	71751
60204	71856	540	0	0	416	0	771	1	696	0	96	72139	798	3	2	71433	25	50755	40620	10134	40100	10000	620291	2743568	0	49	68896	0	71863	71888	63906	3	64176	50100	40200	20000	70200	10000	71786	35	1	1	40201	100	99	100	10000	30100	10000	100	10905	136	495	10630	244	7	922	50	14	10915	117	2	119	0	3	0	2610	1	57	1	1	71573	40464	1076	1033	1046	10000	50100	71796	71621	71705	71801	71899
60204	71953	539	0	0	426	0	817	1	768	0	56	71920	785	2	1	71942	25	50775	40632	10120	40100	10000	621689	2749116	0	49	68611	0	72030	71900	64140	3	64472	50100	40200	20000	70200	10000	71814	35	1	1	40201	100	99	100	10000	30100	10000	100	10907	139	454	10641	254	6	932	48	11	10908	121	2	133	0	9	0	2610	1	57	1	1	71745	40540	1138	1055	1037	10000	50100	71758	71825	71821	71679	71855
60204	71686	540	0	0	389	0	837	1	752	0	92	71736	775	2	2	71343	25	50685	40620	10125	40100	10000	619133	2743698	0	49	68755	0	71855	71926	64180	3	64294	50100	40200	20000	70551	10000	72049	35	1	1	40201	100	99	100	10000	30100	10000	100	10912	145	491	10622	272	7	929	48	20	10883	122	3	123	0	9	0	2610	1	57	1	1	71606	40504	1077	1109	1048	10000	50100	71868	71947	71728	71810	71884
60204	71995	539	0	1	456	0	815	1	704	0	68	71854	783	2	2	71574	25	50675	40624	10127	40100	10000	620015	2754553	0	49	68807	0	71799	72049	63951	3	64325	50100	40200	20000	70200	10000	71681	35	1	1	40201	100	99	100	10000	30100	10000	100	10908	162	483	10661	276	9	914	132	8	10897	119	2	132	3	3	0	2610	1	57	1	1	71504	40504	1037	1043	941	10000	50100	71874	71968	71838	71847	71934

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1943

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	72161	539	2	0	0	0	0	0	438	833	1	752	2	80	71731	849	1	4	71683	25	50655	40482	10129	40010	10000	619102	2750313	0	0	49	68802	71902	71963	64229	3	64162	50010	40020	20102	70020	10000	72082	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10922	1	152	466	10650	260	9	978	32	29	10906	128	2	145	0	1	3	2520	2	64	3	3	71842	40552	1139	1040	1153	10000	50010	71974	72101	72022	71878	72017
60024	71847	540	2	0	0	0	0	0	442	806	1	712	2	108	72129	789	1	1	71659	25	50645	40534	10124	40010	10000	619525	2738920	0	1	49	68974	71895	71893	64270	3	64394	50010	40020	20000	70020	10000	71921	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10910	2	153	494	10665	264	8	942	44	22	10905	129	3	133	2	0	5	2520	1	64	1	1	71727	40568	1082	1155	1057	10000	50010	71842	71797	72020	72153	71917
60024	71975	539	2	0	0	2	0	0	454	815	1	696	2	64	71979	800	1	2	71641	25	50660	40582	10145	40010	10000	618193	2746211	0	1	49	68916	71964	71871	64318	3	64355	50010	40020	20000	70020	10000	71870	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10880	2	137	505	10636	268	6	885	94	18	10903	126	4	143	2	3	9	2520	1	64	1	2	71799	40524	1173	1073	1077	10000	50010	71993	72056	71947	71973	72009
60024	71909	538	2	0	0	0	0	0	428	775	1	736	2	136	71847	797	2	1	71720	43	50670	40586	10135	40010	10000	617455	2749841	0	1	49	68964	71920	72005	64188	3	64488	50010	40020	20000	70020	10000	71991	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10942	3	149	461	10641	258	8	907	66	25	10926	139	4	159	2	3	5	2520	1	64	4	4	71883	40592	1172	1066	1088	10000	50010	71979	72119	71993	71921	71927
60024	71846	538	3	0	0	0	0	0	434	845	1	720	3	104	72059	798	3	2	71832	25	50680	40538	10118	40010	10000	619966	2749921	0	0	49	68957	71794	71916	64218	3	64451	50010	40020	20000	70020	10000	71903	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10924	3	135	482	10653	275	10	968	52	22	10948	118	4	143	3	0	3	2520	4	64	3	3	71856	40512	1136	1036	1090	10000	50010	72016	72098	71907	72158	71837
60024	71895	538	3	0	0	1	0	0	439	816	1	728	3	108	71969	802	2	1	71931	25	50615	40566	10131	40010	10000	617392	2750448	0	1	49	69049	72011	71848	64206	3	64402	50010	40020	20000	70020	10000	71996	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10921	3	141	512	10659	254	11	881	50	23	10915	138	4	138	2	0	13	2520	1	64	3	3	71564	40576	1103	1122	1082	10000	50010	71855	71991	71883	72030	72187
60024	72111	540	3	0	0	0	0	0	437	821	1	744	3	132	71824	804	1	2	71773	25	50595	40574	10134	40010	10000	618850	2753261	0	1	49	69238	71919	71991	64149	3	64314	50010	40020	20000	70020	10000	71985	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10932	4	125	466	10652	266	8	915	68	26	10902	132	5	149	4	3	6	2520	1	64	1	1	71821	40544	1163	1129	1067	10000	50010	71965	71763	72037	72018	72000
60024	71835	538	4	0	0	0	0	0	391	820	1	712	2	100	71822	771	2	1	71844	25	50685	40502	10119	40010	10000	619264	2752885	0	1	49	68828	71840	71990	64126	3	64545	50010	40020	20000	70020	10000	71913	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10895	17	164	478	10654	279	15	916	52	20	10940	131	3	153	2	0	3	2520	1	64	1	1	71761	40556	1135	1020	1096	10000	50010	71948	71876	71932	71757	72031
60024	71844	538	4	0	4	0	0	0	404	803	1	720	3	156	72076	803	1	1	71765	25	50700	40542	10120	40010	10000	619345	2751914	0	1	49	69123	71941	71991	63985	3	64361	50010	40020	20000	70020	10000	71908	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10916	4	142	507	10670	275	8	933	28	15	10917	128	4	142	3	0	4	2520	1	64	1	1	71745	40488	995	1037	1093	10000	50010	71911	72077	71989	71805	72108
60024	71979	539	3	0	0	0	0	0	385	840	1	728	4	108	71896	815	1	1	71781	25	50665	40514	10140	40010	10000	620587	2747981	1	1	49	68799	71994	71958	64202	3	64319	50010	40020	20000	70020	10000	71848	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10939	3	151	488	10654	284	8	915	76	26	10888	114	4	144	3	3	7	2520	1	64	2	1	71914	40548	1062	1223	1232	10000	50010	72057	72135	72079	71950	71985

Test 4: throughput

Count: 8

Code:

  ldpsw x0, x1, [x6], #8
  ldpsw x0, x1, [x7], #8
  ldpsw x0, x1, [x8], #8
  ldpsw x0, x1, [x9], #8
  ldpsw x0, x1, [x10], #8
  ldpsw x0, x1, [x11], #8
  ldpsw x0, x1, [x12], #8
  ldpsw x0, x1, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3934

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240209	32013	239	0	0	0	0	0	0	0	0	0	6472	0	810	1	664	86	68	31355	742	356	2026	1983	1317	25	160118	80129	80000	80100	80000	400580	657941	1	16	49	28544	31635	31479	1290	172	3	1503	160100	80200	160000	80200	80000	31513	38	1	1	80201	100	99	13	100	80000	100	80000	100	80891	16	405	5033	85281	655	12	868	24	4493	86024	791	110	4695	5145	33	0	3	5112	4	16	4	4	31632	29	80022	410	298	8	80000	160100	31355	31581	31623	31501	31321
240204	31489	235	0	0	0	0	0	0	0	0	0	6370	0	757	1	672	86	116	31543	743	333	2150	2246	1297	25	160120	80124	80000	80100	80000	400577	628001	1	15	49	28359	31538	31405	1329	113	3	1352	160100	80200	160000	80200	80000	31405	38	1	1	80201	100	99	18	100	80000	100	80000	100	80835	0	431	5184	84928	737	13	861	36	4896	84886	742	136	5052	4874	16	0	4	5110	4	16	4	3	31306	38	80018	507	436	3	80000	160100	31483	31658	31579	31434	31561
240204	31440	236	0	0	0	0	0	0	1	0	0	6387	0	777	1	744	85	96	31464	742	318	1977	2047	1169	25	160125	80116	80000	80100	80000	400581	663817	1	24	49	28499	31537	31544	1126	115	3	1480	160100	80200	160000	80200	80000	31340	38	1	1	80201	100	99	11	100	80000	100	80000	100	80961	16	408	5443	84940	762	12	906	138	4693	85175	774	122	5273	4935	0	0	6	5110	4	16	5	3	31383	19	80026	398	402	1	80000	160100	31724	31367	31387	31444	31395
240204	31285	235	1	0	0	0	0	0	1	0	0	6648	0	790	1	680	96	144	31531	728	320	2231	1960	1233	25	160114	80119	80000	80100	80000	400600	665476	1	18	49	28343	31403	31576	1315	219	3	1349	160100	80200	160000	80200	80000	31504	38	1	1	80201	100	99	6	100	80000	100	80000	100	80950	16	436	5903	84670	740	12	947	132	5039	85614	768	121	5197	4819	0	1	13	5110	3	16	4	4	31620	31	80027	364	374	2	80000	160100	31563	31413	31407	31534	31820
240204	31519	236	0	0	0	0	0	1	0	0	0	6641	0	777	1	664	79	116	31548	800	357	1941	2000	1398	25	160127	80120	80000	80100	80000	400551	667673	1	21	49	28356	31532	31515	1372	110	3	1618	160100	80200	160000	80200	80000	31542	38	1	1	80201	100	99	11	100	80000	100	80000	100	80868	0	424	5177	85151	734	18	913	32	4811	86054	764	113	4752	4989	0	0	3	5110	4	16	4	4	31419	27	80033	428	391	6	80000	160100	31362	31371	31426	31459	31487
240204	31658	237	1	0	0	0	0	0	0	0	0	6404	0	820	1	696	75	72	31525	775	313	1991	2058	1272	25	160127	80116	80000	80100	80000	400578	657761	1	14	49	28464	31352	31363	1199	313	3	1299	160100	80200	160000	80200	80000	31553	38	1	1	80201	100	99	13	100	80000	100	80000	100	80862	0	393	4677	84682	747	15	846	80	4877	85595	793	106	5188	4659	0	0	3	5110	4	16	4	4	31332	24	80023	379	404	0	80000	160100	31874	31652	31710	31614	31406
240204	31522	236	2	0	0	0	0	0	1	0	0	6480	0	789	1	672	91	220	31533	771	347	2246	2138	1501	25	160124	80123	80000	80100	80000	400557	660148	1	26	49	28268	31616	31489	1285	170	3	1389	160100	80200	160000	80200	80000	31437	38	1	1	80201	100	99	12	100	80000	100	80000	100	80901	31	396	5509	84761	750	12	858	70	4648	85744	845	121	4756	4987	16	0	3	5110	4	16	3	4	31604	39	80026	416	363	5	80000	160100	31511	31565	31332	31504	31481
240204	31727	238	1	0	0	0	0	0	1	0	0	6297	0	810	1	664	101	136	31357	772	344	2033	2044	1277	25	160121	80123	80000	80100	80000	400537	658267	1	12	49	28332	31540	31330	1454	168	3	1594	160100	80200	160000	80200	80000	31470	38	1	1	80201	100	99	12	100	80000	100	80000	100	80944	33	369	5328	84898	712	16	884	166	5027	85845	756	112	5203	4908	32	0	3	5110	4	16	4	4	31620	19	80029	313	408	6	80000	160100	31449	31497	31429	31516	31699
240204	31522	236	1	0	1	0	1	0	1	0	0	6441	0	796	1	672	86	108	31509	760	332	1875	2204	1214	25	160121	80123	80000	80100	80000	400554	645658	1	28	49	28295	31614	31438	1282	146	3	1437	160100	80200	160000	80200	80115	31631	38	1	1	80201	100	99	12	100	80000	100	80000	100	81005	16	396	5067	85082	764	15	942	74	5119	85843	782	121	5150	4421	32	0	0	5112	4	16	6	4	31531	26	80024	374	392	7	80000	160100	31510	31499	31438	31456	31333
240204	31355	238	2	0	0	0	1	0	0	0	0	6836	0	747	1	696	72	80	31452	766	357	1826	1751	1283	25	160127	80128	80000	80100	80000	400557	656393	1	24	49	28344	31610	31218	1211	131	3	1338	160100	80200	160000	80200	80000	31310	38	1	1	80201	100	99	6	100	80000	100	80000	100	80942	17	377	5399	84714	747	11	825	32	4623	85906	751	125	4830	4932	33	0	5	5110	4	16	4	4	31416	24	80030	422	349	3	80000	160100	31516	31635	31581	31426	31463

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3953

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240029	31770	236	0	0	0	0	6853	803	1	688	128	100	31536	795	413	1827	1724	1544	25	160038	80033	80000	80010	80000	400128	680844	1	21	49	28632	31836	31714	1503	109	3	1790	160010	80020	160000	80020	80000	31563	38	1	1	80022	10	9	32	10	80000	10	80000	0	10	80868	363	6569	85754	612	11	906	34	4740	85601	774	127	5017	5333	6	9	5020	0	0	0	3	15	0	0	0	1	1	31549	25	80019	642	519	4	80000	160010	31691	31691	31537	31538	31605
240024	31710	237	0	0	0	0	6684	758	1	696	141	128	31523	768	432	1840	2009	1532	25	160029	80028	80000	80010	80000	400125	670087	1	25	49	28609	31664	31523	1622	169	3	1567	160010	80020	160000	80020	80000	31510	38	1	1	80021	10	9	49	10	80000	10	80000	0	10	80860	357	5696	85465	614	12	942	68	4688	86058	706	131	4846	4906	0	5	5020	0	0	0	1	15	0	0	0	1	1	31502	27	80034	557	474	1	80000	160010	31676	31616	31722	31637	31575
240024	31626	238	0	0	0	0	6971	793	1	672	94	96	31624	733	406	1868	1984	1377	25	160026	80039	80000	80010	80000	400115	672811	0	21	49	28635	31531	31668	1670	96	3	1397	160010	80020	160000	80020	80000	31570	38	1	1	80021	10	9	45	10	80000	10	80000	1	10	80856	365	5404	85140	657	11	907	32	5575	86086	682	124	5127	5102	3	0	5020	0	0	0	1	15	0	0	0	1	1	31590	28	80025	560	562	4	80000	160010	31582	31663	31550	31455	31768
240024	31622	236	0	0	0	0	6627	753	1	656	111	84	31831	759	431	1775	1532	1647	25	160030	80029	80000	80010	80000	400128	653229	1	12	49	28793	31558	31827	1449	107	3	1726	160010	80020	160000	80020	80000	31885	38	1	1	80021	10	9	43	10	80000	10	80000	0	10	80887	388	5486	84763	599	12	857	90	5436	86087	765	144	5292	5642	0	4	5020	0	0	0	1	15	0	0	0	1	1	31789	27	80031	545	568	3	80000	160010	31502	31646	31689	31826	31738
240024	31682	238	0	0	0	0	6450	775	1	704	118	100	31545	781	404	1923	2054	1675	25	160032	80034	80000	80010	80000	400110	687477	1	26	49	28891	31534	31611	1410	102	3	1673	160010	80020	160000	80020	80000	31721	38	1	1	80021	10	9	49	10	80000	10	80000	0	10	80902	418	6181	85871	612	9	882	36	4643	86011	750	126	4694	5103	0	0	5020	0	0	0	1	15	0	0	0	1	1	31593	20	80026	609	611	3	80000	160010	31785	31782	31760	31747	31907
240024	31797	236	0	0	0	0	7012	775	1	704	116	92	31627	763	427	1753	1802	1717	25	160035	80037	80000	80010	80000	400120	676226	0	18	49	28892	31580	31618	1500	85	3	1711	160010	80020	160000	80020	80000	31831	38	1	1	80021	10	9	58	10	80000	10	80000	0	10	80985	345	5746	85145	598	11	854	124	5308	85994	801	109	4901	4890	0	4	5020	0	0	0	1	16	0	0	0	2	2	31638	26	80023	637	471	5	80000	160010	31631	31722	31352	31529	31667
240024	31419	238	0	0	0	0	6427	831	1	680	107	96	31821	754	409	1942	1713	1340	25	160038	80023	80000	80010	80000	400134	645949	1	23	49	28678	31696	31594	1399	101	3	1515	160010	80020	160000	80020	80000	31622	38	1	1	80021	10	9	38	10	80000	10	80000	0	10	80900	378	5699	85455	588	12	844	46	5904	86181	680	118	4907	6132	6	8	5020	0	0	0	1	15	0	0	0	1	1	31796	22	80022	555	518	2	80000	160010	31509	31637	31672	31623	31622
240024	31888	235	0	0	0	0	7210	744	1	696	103	104	31754	751	394	1763	1850	1589	25	160030	80032	80000	80010	80000	400128	658691	0	22	49	28378	31870	31987	1466	89	3	1669	160010	80020	160000	80020	80000	31616	38	1	1	80021	10	9	31	10	80000	10	80000	0	10	80858	368	5083	84787	626	12	868	26	5223	86301	604	117	5307	4823	0	8	5020	0	0	0	1	16	0	0	0	1	1	31561	45	80016	557	607	9	80000	160010	31786	31554	31603	31721	31775
240024	31505	237	1	0	0	0	6492	758	1	680	119	96	31614	778	420	1676	2035	1664	25	160024	80031	80000	80010	80000	400139	682882	1	20	49	28701	31528	31665	1557	125	3	1808	160010	80020	160000	80132	80113	31650	38	1	1	80021	10	9	36	10	80000	10	80000	0	10	80881	364	5832	85047	580	11	874	86	5218	86133	726	119	5064	4819	0	4	5020	0	0	0	1	15	0	0	0	1	1	31644	28	80028	602	575	2	80000	160010	31708	31649	31677	31657	31774
240024	31610	236	0	0	0	0	7014	798	1	704	124	240	31661	761	396	1982	1793	1365	25	160031	80037	80000	80010	80000	400118	681911	1	26	49	28781	31701	31764	1542	67	3	1553	160010	80020	160000	80020	80000	31641	38	1	1	80021	10	9	45	10	80000	10	80000	0	10	80843	371	5734	85258	626	11	860	32	5289	86544	667	126	5260	4872	0	3	5020	0	0	0	1	16	0	0	0	1	1	31624	31	80014	582	607	3	80000	160010	31585	31266	31667	31640	31654

LDPSW (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations