Firestorm: LDR (64-bit) measurements

Code:

  ldr x0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	0	0	0	65	1	0	3	383	2	18	18	16	25	1000	1000	1000	15375	398	399	221	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	19	42	1058	1	1	59	1038	6	1	57	42	19	1	73	2	16	1	1	396	9	9	2	1000	400	400	400	400	400
1004	399	3	1	1	0	0	1	65	1	0	2	384	2	18	18	16	25	1000	1000	1000	15375	398	398	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1021	19	42	1057	1	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	395	9	9	2	1000	400	400	399	400	400
1004	399	3	1	1	0	0	0	65	0	0	2	384	2	18	18	16	25	1000	1000	1000	15375	398	399	222	3	257	1000	1000	1000	402	81	1	1	1001	1000	1000	0	1020	20	42	1057	1	1	58	1038	6	1	57	41	19	0	73	1	16	1	1	395	9	9	2	1000	400	399	400	400	400
1004	399	3	1	0	0	0	0	65	0	0	2	383	2	18	18	16	25	1000	1000	1000	15315	399	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	19	42	1057	0	0	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	9	9	2	1000	400	399	400	400	400
1004	399	3	1	0	0	1	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15375	398	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	20	42	1057	0	2	59	1038	6	1	57	41	19	1	73	1	16	1	1	396	9	9	2	1000	400	400	399	400	400
1004	399	3	1	0	0	0	0	66	0	0	3	384	2	18	18	16	25	1000	1000	1000	15334	399	398	222	3	257	1000	1000	1000	399	82	1	1	1001	1000	1000	0	1020	21	42	1057	1	0	59	1037	6	1	57	42	19	0	73	1	16	1	1	395	9	9	2	1000	399	400	400	400	400
1004	399	3	1	0	0	0	0	65	1	0	3	384	2	18	18	15	25	1000	1000	1000	15357	399	399	222	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1020	19	42	1057	1	0	59	1038	6	1	57	42	19	0	73	1	16	1	1	395	9	9	2	1000	400	399	400	400	400
1004	399	3	1	0	1	0	0	65	1	0	3	385	2	18	18	16	25	1000	1000	1000	15349	399	399	221	3	260	1000	1000	1000	402	82	1	1	1001	1000	1000	0	1018	20	42	1057	1	2	59	1038	6	1	57	42	19	0	73	1	16	1	1	396	9	9	2	1000	400	402	400	400	399
1004	398	3	1	0	0	0	0	65	0	0	2	384	2	18	18	16	25	1000	1000	1000	15362	399	400	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	20	42	1056	1	0	60	1038	6	1	57	42	19	0	73	1	16	1	1	396	9	9	2	1000	400	400	400	399	401
1004	399	3	1	1	0	0	0	65	1	0	3	384	2	18	18	16	25	1000	1000	1000	15307	398	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	20	42	1057	1	1	59	1039	6	1	57	42	19	3	73	1	16	1	1	396	9	9	2	1000	400	399	400	400	400

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70035	525	0	1	0	1	0	0	1	0	1	0	70035	69781	59706	25	40104	30103	10001	30100	10000	616005	3342062	1	49	66970	70050	70050	64643	22	65016	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	15	10000	1	0	1	2610	2	71	1	1	69798	30003	6	6	0	10000	30100	70036	70036	70048	70051	70055
40204	70052	524	0	0	0	0	0	0	1	0	1	0	70035	69764	59709	25	40100	30100	10001	30100	10000	616005	3342206	1	49	66970	70035	70035	64646	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10001	0	3	0	0	10000	1	0	1	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70051	70051	70051	70051	70051
40204	70035	525	0	0	0	0	0	0	1	0	1	0	70035	69781	59709	25	40100	30100	10001	30100	10000	616175	3342206	0	49	66970	70035	70050	64631	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	29	0	0	10000	1	0	1	2610	1	71	1	1	69815	30003	6	0	9	10000	30100	70051	70048	70051	70036	70067
40204	70035	524	0	0	0	0	0	0	1	0	1	0	70035	69781	59709	25	40100	30100	10000	30100	10000	616175	3342206	1	49	66970	70050	70035	64646	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	65	0	0	10000	0	0	0	2610	1	71	1	1	69810	30003	0	6	0	10000	30100	70036	70051	70051	70036	70103
40204	70035	525	0	0	0	0	0	0	0	0	1	0	70035	69735	59709	25	40100	30103	10000	30100	10000	616175	3341470	0	49	66970	70035	70047	64631	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	45	0	3	10007	0	0	1	2610	1	71	1	1	69813	30003	9	0	9	10000	30100	70036	70051	70048	70036	70062
40204	70047	525	0	0	0	0	0	0	1	0	1	0	70032	69781	59709	25	40104	30103	10001	30100	10000	616005	3341470	1	49	66970	70035	70035	64643	3	64953	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	50	0	0	10000	0	0	0	2610	1	71	1	1	69798	30003	6	0	0	10000	30100	70048	70036	70036	70036	70036
40204	70047	525	0	0	0	0	0	0	1	0	0	0	70035	69781	59709	25	40100	30100	10000	30100	10000	616015	3342206	1	49	66975	70035	70035	64646	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	61	0	0	10000	1	0	1	2610	1	71	1	1	69810	30000	0	6	6	10000	30100	70048	70048	70048	70036	70059
40204	70047	524	0	0	0	0	0	0	6	0	1	0	70032	69781	59709	25	40104	30100	10000	30100	10000	616005	3342206	0	49	66970	70055	70035	64643	3	64953	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	35	0	0	10000	1	0	1	2610	1	71	1	1	69810	30000	6	6	6	10000	30100	70036	70048	70048	70048	70110
40204	70047	525	0	0	0	0	0	0	1	0	1	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3341470	1	49	66967	70047	70047	64631	3	64938	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	34	0	0	10000	0	0	0	2610	1	71	1	1	69813	30003	6	0	6	10000	30100	70049	70048	70036	70036	70072
40204	70035	525	0	0	0	0	0	0	6	0	1	0	70035	69764	59709	37	40100	30103	10001	30100	10000	616175	3341470	1	49	66967	70035	70035	64643	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	65	0	0	10000	1	0	1	2610	1	71	1	1	69798	30000	6	6	0	10000	30100	70036	70036	70048	70048	70072

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	0	0	0	0	0	70035	69728	59706	25	40014	30013	10001	30010	10000	616982	3341470	0	49	66970	70081	70051	64665	3	64975	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	4	0	10000	1	0	2520	3	71	3	2	69798	30000	9	0	0	10000	30010	70036	70048	70048	70048	70086
40024	70047	524	1	0	0	1	0	0	70020	69728	59706	25	40010	30010	10001	30010	10000	616952	3341470	0	49	66967	70035	70047	64653	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	33	0	10000	1	1	2520	2	71	3	3	69810	30000	6	6	0	10000	30010	70048	70036	70036	70036	70052
40024	70104	524	0	0	0	1	1	0	70032	69728	59706	25	40010	30010	10001	30010	10000	617068	3342062	0	49	66967	70047	70035	64653	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	42	0	10000	1	1	2520	3	71	3	3	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70071
40024	70035	524	0	0	0	0	1	0	70035	69728	59695	25	40010	30013	10001	30010	10000	617077	3342062	0	49	66955	70047	70050	64665	3	65097	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	35	0	10000	0	1	2520	2	71	3	3	69810	30003	9	6	0	10000	30010	70036	70048	70048	70036	70086
40024	70035	524	0	0	0	1	0	0	70020	69743	59695	25	40010	30013	10001	30010	10000	617068	3342062	0	49	66970	70035	70035	64653	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	56	0	10000	0	1	2520	2	71	5	3	69810	30003	6	6	9	10000	30010	70048	70048	70048	70048	70043
40024	70047	525	0	0	0	1	1	0	70035	69728	59706	25	40014	30013	10000	30010	10000	616952	3342062	0	49	66967	70047	70047	64668	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	32	0	10000	1	0	2520	3	71	3	3	69798	30000	6	6	0	10000	30010	70036	70048	70036	70048	70083
40024	70047	524	0	0	0	0	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616982	3342062	0	49	66955	70050	70035	64665	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	41	0	10000	0	1	2520	3	71	2	3	69810	30003	9	6	6	10000	30010	70048	70051	70048	70036	70049
40024	70137	525	0	0	0	1	1	0	70032	69728	59695	25	40010	30013	10000	30010	10000	616952	3342062	0	49	66955	70047	70047	64653	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	70	0	10000	1	1	2520	3	71	3	3	69798	30003	0	6	6	10000	30010	70051	70048	70048	70036	70067
40024	70047	525	0	0	0	0	0	0	70020	69760	59695	25	40014	30013	10001	30010	10000	616952	3341470	0	49	66967	70043	70050	64653	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	36	0	10000	0	1	2520	3	71	3	2	69810	30003	0	6	0	10000	30010	70048	70051	70048	70048	70134
40024	70047	525	0	1	1	0	0	0	70020	69728	59706	25	40010	30013	10001	30010	10000	616952	3342062	0	49	66970	70047	70047	64653	3	64972	40010	30020	10000	60020	10000	70049	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	40	0	10000	0	1	2520	3	71	3	2	69813	30000	0	0	0	10000	30010	70048	70048	70036	70048	70107

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	1	0	0	0	0	45	1	1	26712	2	12	12	50	25	80100	100	80000	100	80000	500	1167578	1	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	1	0	42	80000	6	1	39	43	5110	1	16	1	1	26724	0	10	4	80000	100	26728	26708	26945	26756	26736
80204	26727	200	0	0	0	0	1	0	45	0	1	26692	0	12	12	24	25	80100	100	80130	100	80000	500	1166525	1	49	23647	26741	26734	16633	3	16665	80278	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80171	5	0	39	80039	0	0	39	43	5110	1	16	1	1	26724	10	10	4	80000	100	26708	26728	26958	26735	26731
80204	26727	201	0	0	0	0	0	0	0	0	1	26712	2	12	12	70	25	80100	100	80000	100	80000	500	1166525	1	49	23647	26707	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	2	0	40	80039	6	1	39	43	5110	1	16	1	1	26704	0	0	0	80000	100	26728	26708	26728	26874	26735
80204	26741	200	0	0	0	0	0	0	45	1	1	26712	0	12	12	16	49	80232	100	80000	100	80000	500	1167231	1	49	23647	26727	26727	16650	3	16665	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	1	0	39	80000	6	0	39	0	5110	1	16	1	1	26724	10	10	0	80000	100	26728	26728	26728	26823	26734
80204	26727	200	0	0	0	0	0	0	0	1	1	26712	0	0	12	88	25	80100	100	80000	100	80000	500	1166525	1	49	23627	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	1	0	39	80000	6	1	0	43	5110	1	16	1	1	26704	0	0	4	80000	100	26708	26728	26728	26847	26733
80204	26727	200	0	0	0	1	1	0	45	1	1	26692	2	0	0	84	25	80100	100	80000	100	80000	500	1166525	1	49	23647	26707	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80000	1	0	39	80039	6	1	0	43	5110	1	16	1	1	26724	10	10	4	80000	100	26728	26728	26737	26834	26736
80204	26727	200	0	0	0	0	0	0	45	1	1	26716	2	0	12	89	25	80100	100	80000	100	80000	500	1167231	1	49	23647	26707	26727	16630	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	22	0	42	80039	6	1	0	43	5110	1	16	1	1	26724	10	0	4	80000	100	26708	26728	26737	26866	26729
80204	26727	200	0	0	0	0	0	0	45	0	1	26692	0	0	12	71	25	80100	100	80000	100	80000	500	1165789	1	49	23647	26707	26727	16630	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	1	0	39	80039	6	1	39	43	5110	1	16	1	1	26724	10	10	0	80000	100	26728	26728	26738	26828	26732
80204	26755	200	0	0	0	0	1	0	45	1	1	26692	2	12	0	43	25	80100	100	80000	100	80000	500	1167231	1	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	42	80039	0	0	39	80039	6	1	0	43	5110	1	16	1	1	26724	10	10	4	80000	100	26728	26728	26912	26780	26728
80204	26727	200	0	0	0	0	0	0	45	1	0	26712	2	0	12	16	25	80100	100	80000	100	80000	500	1166525	1	49	23627	26707	26727	16630	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80000	6	1	39	43	5110	1	16	1	1	26724	0	11	4	80000	100	26728	26728	26918	26746	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	1	1	1	1	1	21	1	0	3	26721	3	7	7	74	25	80010	10	80000	10	80000	50	1168239	1	49	23657	26736	26715	16660	3	16717	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80021	18	43	80019	0	2	0	22	80040	6	1	19	43	19	0	0	5020	7	16	0	6	4	26734	13	0	5	80000	10	26715	26737	26737	26737	26743
80024	26736	200	1	1	1	0	0	0	70	1	0	0	26722	2	0	9	3	25	80010	10	80000	10	80000	50	1165304	1	49	23635	26737	26736	16659	3	16695	80010	20	80000	20	80000	26737	64	1	1	80021	10	9	0	10	80000	10	80000	1	10	80019	19	0	80059	1	40	0	153	80039	6	1	58	43	19	1	0	5020	5	16	0	4	6	26733	0	13	5	80000	10	26716	26737	26737	26738	26892
80024	26743	200	1	0	1	0	0	0	22	1	0	3	26722	0	7	7	31	25	80010	10	80000	10	80000	50	1167939	1	49	23657	26718	26739	16684	3	16716	80010	20	80000	20	80192	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	80058	0	0	0	63	80040	0	1	58	43	19	1	0	5020	8	16	0	8	6	26733	13	13	5	80000	10	26738	26738	26715	26814	26737
80024	26736	200	1	1	0	0	0	0	67	0	0	3	26700	2	7	7	55	25	80010	10	80000	10	80000	50	1167106	1	49	23657	26715	26737	16681	3	16694	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	0	80058	1	0	1	63	80040	0	1	19	0	19	1	0	5020	8	16	0	8	6	26733	13	0	0	80000	10	26716	26737	26737	26916	26741
80024	26744	200	1	1	0	0	0	0	21	0	0	2	26721	3	0	7	55	25	80010	10	80000	10	80000	50	1167736	1	49	23656	26715	26737	16681	3	16716	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	19	43	80059	0	0	0	61	80000	6	1	19	0	19	1	0	5020	8	16	0	8	6	26733	13	0	0	80000	10	26737	26737	26738	26810	26723
80024	26715	200	1	0	1	0	0	0	67	1	0	3	26722	0	7	0	71	25	80010	10	80000	10	80000	50	1166960	1	49	23656	26736	26737	16681	3	16716	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	80061	0	1	1	61	80039	6	1	58	0	19	0	0	5020	7	16	0	5	7	26736	0	13	5	80000	10	26737	26737	26738	26816	26746
80024	26736	200	1	0	0	0	0	0	67	0	0	3	26699	2	0	7	92	25	80010	10	80000	10	80000	50	1165304	1	49	23656	26737	26715	16681	3	16716	80010	20	80000	20	80000	26714	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	80019	0	1	0	64	80040	6	0	19	0	19	0	0	5020	6	16	0	6	8	26733	13	13	0	80000	10	26716	26737	26738	26784	26746
80024	26736	200	1	0	0	1	0	0	67	1	0	2	26722	2	0	9	85	25	80010	10	80000	10	80000	50	1173975	1	49	23656	26737	26736	16659	3	16695	80010	20	80000	20	80000	26715	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	0	80059	1	2	1	61	80040	0	1	58	0	19	0	0	5020	6	16	0	8	6	26733	0	0	5	80000	10	26737	26737	26737	26801	26746
80024	26715	200	1	0	0	0	0	0	21	1	0	0	26722	2	9	7	72	25	80010	10	80000	10	80000	50	1173975	1	49	23635	26737	26737	16681	3	16716	80010	20	80000	20	80000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	43	80058	1	1	0	60	80039	6	0	19	45	19	0	0	5020	8	16	0	8	6	26733	0	13	0	80000	10	26737	26716	26738	26825	26741
80024	26723	200	1	1	1	1	1	1	69	1	0	3	26721	0	7	7	19	25	80010	10	80000	10	80000	50	1166960	1	49	23657	26740	26736	16681	3	16716	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80019	20	43	80019	1	3	1	60	80000	6	1	19	43	19	2	0	5020	4	16	0	5	7	26734	13	13	0	80000	10	26738	26737	26737	26783	26747

LDR (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations