Firestorm: LDR (post-index, 64-bit) measurements

Code:

  ldr x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	1e	20	22	23	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1041	8	1	0	1	1	0	79	22	1	0	0	0	3	0	1025	19	1	7	7	17	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1024	8	0	48	1047	2	1	20	8	31	1024	34	7	31	72	6	0	0	73	1	16	1	1	1037	1000	24	25	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	0	0	1	53	22	0	0	0	0	2	20	1025	0	1	2	1	24	25	2000	1000	1000	1000	1000	52840	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1028	7	0	81	1054	1	1	26	0	48	1024	36	8	31	56	7	0	0	73	1	16	1	1	1037	1000	26	17	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	1	0	70	16	1	0	0	0	3	0	1025	12	3	2	1	16	25	2000	1000	1000	1000	1000	52828	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1028	7	0	59	1044	12	0	24	14	36	1042	40	6	25	40	6	1	0	73	1	16	1	1	1037	1000	24	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	1	1	0	39	16	0	0	0	0	1	0	1025	0	0	0	4	21	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1024	6	0	64	1049	12	2	0	0	31	1038	39	6	24	64	6	4	0	73	1	16	1	1	1037	1000	20	24	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	79	12	1	0	0	0	2	0	1025	16	2	4	4	23	25	2000	1000	1000	1000	1000	52816	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1022	7	0	46	1045	1	0	37	8	31	1046	39	6	29	48	6	1	29	73	1	16	1	1	1037	1000	24	17	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	79	16	1	0	0	3	6	0	1025	12	2	8	3	24	25	2000	1000	1000	1000	1000	52844	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1037	21	0	53	1038	4	1	13	4	28	1034	28	6	33	80	7	1	0	73	1	16	1	1	1037	1000	48	31	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	1	1	85	0	0	0	0	0	3	0	1025	8	2	4	8	22	25	2000	1000	1000	1000	1000	52840	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1025	6	0	74	1052	4	1	39	0	24	1025	40	4	27	64	6	1	0	73	1	16	1	1	1037	1000	49	35	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	0	1	0	62	22	2	0	0	0	2	0	1025	14	1	4	2	21	25	2000	1000	1000	1000	1000	52832	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1044	9	0	75	1040	9	0	2	14	32	1032	34	6	37	56	7	2	0	73	1	16	1	1	1037	1000	26	24	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	0	1	0	83	12	0	0	0	0	3	0	1025	14	1	7	1	14	25	2000	1000	1000	1000	1000	52832	45825	1	1040	1043	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1023	7	0	58	1042	16	0	17	12	31	1037	34	4	26	40	6	0	0	73	1	16	1	1	1037	1000	39	26	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	1	0	91	22	0	0	0	0	2	4	1025	13	1	4	2	27	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1024	7	1	48	1050	3	0	24	12	41	1029	45	5	36	72	6	2	0	73	1	16	1	1	1037	1000	24	31	1000	1000	1041	1041	1041	1041	1059

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1924

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72089	539	2	1	1	0	0	0	0	416	0	843	1	0	672	3	108	71784	804	5	0	71654	25	50785	40636	10138	40100	10000	615949	2733921	49	68817	72118	72029	65382	0	3	65698	50100	40200	10000	70200	10000	71903	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10924	2	113	509	10700	271	12	919	52	22	10910	126	12	122	2	0	10	0	2610	2	57	1	1	71831	40552	1062	1057	1082	10000	40100	72049	71970	72071	71994	72010
50204	72051	540	1	0	0	0	0	0	0	461	0	841	1	0	584	1	124	71929	830	7	2	71539	25	50785	40620	10128	40100	10000	614988	2725821	49	68902	72057	71657	65336	0	3	65488	50100	40200	10000	70200	10000	71916	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10907	1	161	498	10674	274	15	900	52	34	10917	120	9	133	1	0	7	0	2610	1	58	1	1	71739	40564	1078	1133	1042	10000	40100	72042	71894	71798	71789	71910
50204	71868	538	1	0	0	0	0	0	0	482	0	821	1	0	712	1	92	71962	789	8	2	71528	25	50765	40600	10138	40100	10000	613584	2726163	49	68890	71957	71863	65379	0	3	65449	50100	40200	10000	70200	10000	71970	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10907	2	136	487	10677	237	12	929	178	33	10931	119	10	131	1	3	3	0	2610	1	58	1	1	71672	40552	1072	1138	1128	10000	40100	71914	71903	71838	72021	72024
50204	71886	538	2	0	0	0	0	0	0	451	0	810	1	0	712	1	152	72059	792	7	3	71754	25	50785	40612	10134	40100	10000	615684	2721858	49	69024	71891	71831	65411	0	3	65455	50100	40200	10000	70200	10000	71851	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10923	2	137	493	10654	253	10	920	82	24	10929	128	10	128	2	0	3	0	2610	1	58	1	1	71595	40560	1096	1087	1033	10000	40100	71993	71862	71921	71846	72079
50204	71896	539	1	0	0	0	0	0	0	468	0	833	1	0	704	1	72	71766	802	6	0	71587	25	50775	40664	10143	40100	10000	613432	2728762	49	68902	71965	72000	65312	0	3	65510	50100	40200	10000	70200	10000	71972	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10899	1	135	502	10723	280	15	938	30	28	10911	142	10	129	1	0	3	0	2610	1	78	1	1	71855	40576	972	1167	1080	10000	40100	72039	71894	72034	72008	71897
50204	71873	538	1	0	1	0	0	0	0	455	0	821	1	0	624	1	144	71921	821	8	2	71517	25	50760	40604	10133	40100	10047	617257	2729195	49	68826	71848	71958	65421	0	3	65463	50100	40200	10000	70200	10000	71811	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10906	2	143	475	10743	278	14	897	94	28	10895	139	11	112	2	3	4	0	2610	1	58	1	1	71712	40532	1021	1113	1099	10000	40100	71908	71894	72022	71891	71826
50204	71989	539	1	0	1	0	0	0	0	468	0	846	1	0	544	1	96	71890	804	5	0	71577	25	50785	40660	10125	40100	10000	617257	2730242	49	68951	71959	71994	65441	0	3	65602	50100	40200	10000	70200	10000	71949	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10890	2	140	517	10711	269	27	896	32	24	10929	119	6	135	2	4	5	0	2610	1	17	1	1	71801	40552	1013	1104	1062	10000	40100	71892	72005	71926	71834	71829
50204	71999	540	1	1	0	0	0	0	0	460	0	831	1	0	536	1	112	71857	808	5	0	71626	25	50730	40644	10134	40100	10000	617438	2727854	49	68893	71917	71987	65430	0	3	65559	50100	40200	10000	70200	10000	72146	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10899	1	141	531	10696	268	9	890	142	27	10900	119	10	128	1	0	3	0	2610	1	58	1	1	71807	40568	1038	1022	1097	10000	40100	71940	71921	71988	72067	72075
50204	71856	539	1	1	1	0	0	0	0	410	0	815	1	0	720	1	104	71835	800	7	3	71707	25	50845	40664	10123	40100	10000	615504	2726220	49	68882	71921	71922	65389	0	3	65509	50100	40200	10000	70200	10000	71768	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10922	1	130	469	10660	271	12	920	42	27	10920	120	8	117	1	1	3	0	2610	1	58	1	1	71532	40512	1039	979	1034	10000	40100	71966	71916	71933	72066	72049
50204	71837	539	1	0	0	0	0	0	0	429	0	830	1	0	720	1	100	71865	827	9	3	71712	25	50775	40628	10138	40100	10000	614119	2727916	49	68861	71757	71807	65510	0	3	65645	50100	40200	10000	70200	10000	72094	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10866	4	155	502	10677	287	25	930	102	30	10919	130	11	117	1	0	7	0	2610	1	58	1	1	72006	40549	1191	1072	1067	10000	40100	71852	71856	71628	72000	71984

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.2010

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72195	540	5	1	0	5	0	0	470	841	1	744	6	108	72147	810	13	2	71584	25	50760	40562	10140	40010	10000	612885	2726375	1	49	68850	72220	72016	65546	3	65662	50010	40020	10000	70020	10000	71924	35	1	1	40021	10	9	10	10000	30010	10000	10	10915	5	155	532	10661	288	9	943	80	37	10942	126	15	124	4	3	3	0	0	0	2521	9	85	9	9	72188	40592	1193	1105	1074	10000	40010	72100	72133	72176	72006	71990
50024	72021	541	5	0	0	5	0	0	475	850	1	728	4	120	71924	814	10	3	71993	25	50785	40554	10133	40010	10000	614807	2723110	1	49	68849	72169	71979	65721	3	65690	50010	40020	10000	70020	10000	71910	35	1	1	40021	10	9	10	10000	30010	10000	10	10942	4	149	496	10650	268	10	926	72	43	10928	125	13	135	4	1	7	0	0	0	2521	9	85	8	8	71967	40576	1128	1052	1127	10000	40010	71846	71912	71905	71952	72314
50024	72113	539	4	0	4	0	0	2	510	834	1	720	4	124	72124	800	11	4	71646	25	50690	40582	10143	40010	10000	612147	2733049	1	49	68931	72030	71998	65505	3	65472	50010	40020	10000	70020	10000	72087	35	1	1	40021	10	9	10	10000	30010	10000	10	10880	6	156	511	10651	242	9	964	54	31	10918	122	15	128	4	7	5	0	0	0	2521	9	85	9	10	71721	40604	1084	1048	1015	10000	40010	72050	71984	71868	72150	72019
50024	72001	542	4	0	0	2	0	4	506	810	1	728	5	104	71998	827	11	8	71706	25	50750	40558	10151	40010	10000	613669	2728466	1	49	68896	72054	72021	65450	3	65556	50010	40020	10000	70020	10000	71910	35	1	1	40021	10	9	10	10000	30010	10000	10	10921	4	151	532	10681	264	9	932	50	34	10993	123	15	133	4	0	7	0	0	0	2521	10	85	11	11	71919	40564	1093	1158	990	10000	40010	72133	72221	71976	72192	72028
50024	72113	540	4	0	0	0	0	0	428	866	1	720	4	136	72037	797	12	4	71741	25	50770	40606	10147	40010	10000	613073	2729511	1	49	68912	72168	71933	65522	3	65731	50010	40020	10000	70020	10000	71888	35	1	1	40021	10	9	10	10000	30010	10000	10	10911	5	167	510	10670	277	10	901	48	43	10969	120	17	132	5	0	7	0	0	0	2521	8	85	8	7	72030	40616	1164	1087	1134	10000	40010	71859	72110	72012	71939	72018
50024	71976	539	4	0	4	0	0	0	497	863	1	736	4	136	71980	790	11	4	71800	25	50630	40598	10142	40010	10000	613526	2730158	1	49	69104	72087	72043	65499	3	65625	50010	40020	10000	70020	10000	71912	35	1	1	40021	10	9	10	10000	30010	10000	10	10928	4	154	511	10638	282	7	930	50	37	10961	134	19	137	4	0	7	0	0	0	2521	9	85	8	10	72026	40600	1072	1067	1093	10000	40010	72098	71891	72056	72016	72118
50024	71888	540	4	0	0	0	0	0	436	828	1	712	6	136	72075	812	12	3	71769	25	50725	40530	10142	40010	10000	615265	2728744	1	49	68884	72040	72099	65511	3	65720	50010	40020	10000	70020	10000	72009	35	1	1	40021	10	9	10	10000	30010	10000	10	10899	4	163	508	10630	278	7	934	50	1885	10938	132	17	121	4	0	3	0	0	0	2523	9	85	7	8	71859	40556	1152	1175	1185	10000	40010	72017	72136	71950	71999	72133
50024	71878	540	4	0	0	0	0	4	494	831	1	712	5	108	71932	811	11	1	71811	25	50710	40614	10142	40010	10000	612451	2732464	0	49	69062	71965	72194	65571	3	65720	50010	40020	10000	70020	10000	71883	35	1	1	40021	10	9	10	10000	30010	10000	10	10907	4	139	503	10672	274	8	908	40	38	10929	136	15	129	4	0	9	0	0	0	2521	7	85	9	10	72054	40564	1050	1054	1152	10000	40010	71873	71866	71991	72116	72014
50024	71976	539	4	0	0	0	0	4	443	820	1	720	4	128	71838	817	11	3	71693	25	50725	40590	10138	40010	10000	612737	2728204	1	49	68876	71962	71969	65356	3	65748	50010	40020	10000	70020	10000	72108	35	1	1	40021	10	9	10	10000	30010	10000	10	10918	6	154	507	10661	271	12	930	50	34	10910	129	14	137	4	4	1	0	0	0	2521	10	85	8	8	71884	40556	1199	1111	1162	10000	40010	72006	71957	71906	71988	72080
50024	72085	540	5	0	0	0	0	0	455	809	1	704	4	96	72087	808	10	1	71723	25	50690	40594	10134	40010	10000	614381	2728713	1	49	68918	72094	71924	65514	3	65642	50010	40020	10000	70020	10000	72140	35	1	1	40021	10	9	10	10000	30010	10000	10	10933	10	161	511	10636	279	11	931	50	33	10935	120	18	136	4	14	3	0	0	0	2521	9	85	9	10	71947	40584	1161	1145	1093	10000	40010	72114	72152	72079	72255	72144

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6], #8
  ldr x0, [x7], #8
  ldr x0, [x8], #8
  ldr x0, [x9], #8
  ldr x0, [x10], #8
  ldr x0, [x11], #8
  ldr x0, [x12], #8
  ldr x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3681

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29654	221	3	0	0	1	7371	820	1	728	105	188	29539	801	583	1621	1819	2148	25	160172	80171	80000	80100	80000	400761	1321744	1	63	49	26558	29449	29497	9434	40	3	9519	160100	80200	80000	80200	80000	29601	35	1	1	80201	100	99	25	100	80000	100	80000	0	100	80950	18	421	4824	85374	687	9	922	72	4691	86403	816	134	5068	5576	18	0	3	0	5110	1	16	1	1	29430	29	80055	638	519	124	80000	80100	29493	29338	29353	29354	29463
160204	29495	221	3	0	0	1	6759	837	1	752	133	160	29500	811	582	1839	1847	2179	25	160166	80151	80000	80100	80000	400789	1301061	0	72	49	26711	29337	29557	9371	0	3	9516	160100	80200	80000	80200	80000	29525	35	1	1	80201	100	99	54	100	80000	100	80000	0	100	80934	16	455	4854	85507	634	14	910	50	5075	85904	777	125	5513	4810	0	0	3	0	5110	1	16	1	1	29382	45	80060	565	521	100	80000	80100	29492	29355	29468	29415	29206
160204	29348	220	1	0	0	0	6672	857	1	632	111	144	29355	822	642	1476	1786	2189	25	160162	80159	80000	80100	80000	400801	1316343	1	52	49	26215	29563	29535	9294	0	3	9293	160100	80200	80000	80200	80000	29482	35	1	1	80201	100	99	42	100	80000	100	80000	0	100	80915	0	403	5335	85056	673	13	914	72	5072	86588	725	118	5449	5088	0	0	3	0	5110	1	16	1	1	29447	31	80059	570	534	96	80000	80100	29353	29354	29536	29542	29729
160204	29358	220	2	0	0	0	6791	832	1	712	118	96	29525	822	569	1619	1810	1965	25	160152	80152	80000	80100	80000	400798	1314947	1	86	49	26298	29423	29535	9475	0	3	9301	160100	80200	80000	80200	80000	29243	35	1	1	80201	100	99	49	100	80000	100	80000	0	100	80915	0	415	5059	85195	710	13	900	32	5096	85336	765	127	4974	4906	0	3	3	0	5110	1	16	1	1	29406	18	80062	562	530	96	80000	80100	29552	29688	29394	29375	29323
160204	29383	220	3	0	0	0	6857	844	1	712	112	92	29620	833	628	1594	1658	2283	25	160155	80155	80000	80100	80000	400802	1307726	1	61	49	26473	29407	29511	9284	0	3	9400	160100	80200	80000	80200	80000	29463	35	1	1	80201	100	99	44	100	80000	100	80000	0	100	80937	18	435	5437	85453	699	10	911	76	5498	85185	805	124	4966	5443	0	0	17	0	5110	1	16	1	1	29266	30	80052	666	581	100	80000	80100	29517	29400	29673	29594	29370
160204	29282	220	2	0	0	0	7391	826	1	720	134	148	29436	815	578	1717	1811	2376	25	160151	80166	80000	80100	80000	400785	1321283	1	61	49	26533	29344	29507	9398	0	3	9422	160100	80200	80000	80200	80000	29423	35	1	1	80201	100	99	32	100	80000	100	80000	0	100	80956	0	405	5109	84844	714	8	929	48	5103	86417	786	128	5482	5176	0	3	4	0	5110	1	16	1	1	29442	28	80066	600	605	101	80000	80100	29366	29267	29365	29470	29404
160204	29277	220	3	0	0	0	7222	833	1	776	109	128	29249	817	565	1723	1748	2350	25	160147	80167	80000	80100	80000	400767	1300630	0	57	49	26373	29396	29333	9859	0	3	9632	160100	80200	80000	80200	80000	29305	35	1	1	80201	100	99	62	100	80000	100	80000	0	100	80960	18	413	5903	85115	703	28	970	48	4987	86439	782	122	5002	5688	18	0	4	0	5110	1	16	1	1	29432	29	80059	613	517	102	80000	80100	29402	29426	29512	29311	29303
160204	29483	218	3	0	0	0	6451	822	1	784	135	104	29323	805	573	1688	1568	2051	25	160165	80160	80000	80100	80000	400859	1306182	0	59	49	26235	29604	29483	9512	0	3	9463	160100	80200	80000	80200	80000	29478	35	1	1	80201	100	99	59	100	80000	100	80000	0	100	80902	0	399	5256	84900	647	14	930	32	4797	85595	710	127	5426	4968	0	0	3	0	5110	1	17	1	1	29312	45	80067	552	524	118	80000	80100	29188	29476	29385	29386	29604
160204	29555	222	3	0	0	0	6614	820	1	760	124	116	29501	812	517	1749	1846	2214	25	160169	80164	80000	80100	80000	400783	1303869	1	67	49	26251	29723	29301	9374	0	3	9431	160100	80200	80000	80200	80000	29671	35	1	1	80201	100	99	52	100	80000	100	80000	0	100	80892	0	446	5588	84941	664	10	924	48	5036	86199	707	129	5319	5182	0	0	3	0	5110	1	16	1	1	29539	27	80058	618	530	95	80000	80100	29385	29523	29485	29683	29350
160204	29496	220	3	0	0	0	6767	820	1	712	131	148	29359	798	557	1615	1982	2321	25	160165	80160	80000	80100	80000	400829	1301528	0	65	49	26181	29589	29431	9472	0	3	9470	160100	80200	80000	80200	80000	29391	35	1	1	80201	100	99	60	100	80000	100	80000	0	100	80927	0	437	5119	85649	677	13	934	34	5568	86043	736	131	5029	4946	0	0	0	0	5110	1	17	1	1	29380	27	80048	685	631	96	80000	80100	29611	29513	29306	29486	29464

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3689

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29868	221	2	0	0	0	0	1	7800	0	865	1	736	131	120	29466	803	655	1986	1723	2212	25	160075	80082	80000	80010	80000	400428	1308958	0	1	76	49	26517	0	29534	29546	9352	3	9494	160010	80020	80000	80020	80000	29568	35	1	1	80021	10	9	63	10	80000	10	80000	0	10	80992	28	399	5862	85569	697	12	925	66	5323	87098	744	140	4950	5686	36	0	3	5020	13	16	0	5	4	29557	25	80065	638	570	106	80000	80010	29346	29401	29544	29609	29555
160024	29345	222	2	0	0	0	0	0	7054	0	858	1	760	105	140	29391	809	639	1872	1677	2329	25	160060	80081	80000	80010	80000	400358	1305516	0	0	69	98	26778	0	29637	29442	9379	3	9506	160010	80020	80000	80020	80000	29647	35	1	1	80021	10	9	35	10	80000	10	80000	0	10	80990	26	372	5622	85225	669	12	942	32	5411	85901	831	131	5398	5432	35	0	3	5020	8	16	0	5	6	29427	36	80059	607	568	89	80000	80010	29560	29486	29399	29641	29699
160024	29574	221	2	1	0	0	0	0	6785	0	816	1	728	121	116	29544	803	629	1679	1686	2360	25	160078	80068	80000	80010	80000	400347	1301917	0	0	74	49	26356	0	29399	29354	9364	3	9427	160010	80020	80000	80020	80000	29392	35	1	1	80021	10	9	56	10	80000	10	80000	0	10	80976	33	412	5096	85180	654	17	950	78	4764	85996	803	135	5509	5684	31	2	3	5020	7	16	0	12	6	29752	33	80070	649	618	109	80000	80010	29320	29526	29475	29386	29503
160024	29431	221	2	0	0	0	0	0	7261	0	833	1	760	118	136	29663	810	606	1819	1723	2258	25	160077	80074	80000	80010	80000	400362	1303290	0	0	77	49	26505	0	29418	29538	9486	3	9470	160010	80020	80000	80020	80000	29457	35	1	1	80021	10	9	27	10	80000	10	80000	0	10	80968	36	399	4965	85497	671	10	925	48	5305	86269	824	130	5164	5545	32	0	0	5020	5	16	0	7	12	29773	33	80071	593	525	118	80000	80010	29549	29621	29524	29581	29468
160024	29680	221	2	0	1	0	0	0	7060	0	852	1	744	117	140	29267	817	658	1588	1878	2071	25	160070	80056	80000	80010	80000	400368	1297975	0	1	64	49	26438	0	29484	29443	9380	3	9486	160010	80020	80000	80020	80000	29560	35	1	1	80021	10	9	55	10	80000	10	80000	0	10	80932	27	379	5835	85858	693	10	960	42	5226	86527	841	130	5248	5421	32	14	0	5020	10	16	0	10	6	29460	32	80069	584	546	96	80000	80010	29556	29679	29741	29434	29434
160024	29464	221	2	0	0	0	0	0	7071	0	844	1	712	109	152	29598	816	653	1586	1822	2084	25	160072	80072	80000	80010	80000	400299	1297553	0	0	57	49	26512	0	29481	29695	9516	3	9555	160010	80020	80000	80020	80000	29371	35	1	1	80021	10	9	32	10	80000	10	80000	0	10	80931	26	392	5741	85889	714	14	939	46	5391	86116	808	120	5191	5281	34	0	0	5020	6	16	0	8	6	29395	30	80057	579	607	103	80000	80010	29642	29748	29591	29757	29725
160024	29542	221	2	0	0	2	0	0	6796	0	851	1	768	126	136	29438	836	673	1785	1686	2461	25	160072	80076	80000	80010	80000	400338	1301895	0	1	62	49	26530	0	29567	29437	9308	3	9350	160010	80020	80177	80020	80000	29454	35	1	1	80021	10	9	63	10	80000	10	80000	0	10	80983	35	391	5468	85395	634	16	928	72	5178	86575	777	132	5447	5740	35	0	4	5020	12	15	0	12	11	29463	40	80081	619	584	89	80000	80010	29499	29630	29546	29569	29549
160024	29702	221	2	0	0	0	0	0	7203	108	841	1	712	137	72	29609	823	637	1704	1750	2239	25	160071	80075	80000	80010	80000	400323	1318306	1	1	73	49	26430	0	29395	29618	9286	3	9569	160010	80020	80000	80020	80000	29530	35	1	1	80021	10	9	53	10	80000	10	80000	1	10	80950	34	398	5961	85628	637	7	890	76	5158	86569	831	121	5171	5474	33	0	3	5020	11	16	0	7	11	29642	38	80061	602	505	105	80000	80010	29570	29705	29652	29548	29681
160024	29505	220	2	0	0	0	0	0	7367	0	867	1	744	132	124	29640	829	710	1733	1707	2123	25	160069	80077	80000	80010	80000	400353	1309582	0	1	63	49	26452	0	29492	29504	9414	3	9466	160010	80020	80000	80020	80000	29472	35	1	1	80021	10	9	43	10	80000	10	80000	0	10	80959	32	395	6092	85293	690	11	934	68	5403	86129	742	130	5188	5351	15	0	3	5020	11	16	0	10	10	29526	29	80057	597	546	88	80000	80010	29540	29323	29487	29642	29656
160024	29725	222	2	0	0	0	0	0	7004	0	844	1	720	130	96	29420	802	648	1686	1808	2256	25	160063	80076	80000	80010	80000	400357	1311551	0	1	65	49	26211	0	29324	29631	9457	3	9697	160010	80020	80000	80020	80000	29439	35	1	1	80021	10	9	41	10	80000	10	80000	0	10	80926	31	427	5238	85924	680	16	924	72	5406	86297	821	129	5252	5698	17	0	6	5020	7	16	0	5	9	29310	48	80058	556	621	102	80000	80010	29597	29496	29749	29531	29527

LDR (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations