Firestorm: UDIV (fast, 64-bit) measurements

Code:

  udiv x0, x1, x2

Initialization

  mov x1, #0
  mov x2, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2038	15	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	82	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	84	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	61	950	25	1000	1000	1000	53725	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	2	16	2	2	1981	1000	1000	2039	2039	2039	2039	2039

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0
  mov x2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	675	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	3	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90077	90036
30204	90035	675	0	0	0	0	0	330	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85898	3	86243	30100	30200	60200	90035	343	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	3	0	279	0	128	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86311	30100	30200	60442	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	0	726	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	837	0	2097	81152	25	30100	30100	30432	8527358	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86308	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	34	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90035	675	0	0	0	0	0	0	0	726	81210	25	30010	30010	30108	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	4	0	0	0	0	1890	0	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	1890	0	2	16	2	4	89751	30000	30010	90036	90036	90036	90396	90081
30024	90035	674	0	0	0	1	3	1023	0	600	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	6	0	0	1890	0	2	88	2	2	89944	30015	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	0	903	0	61	81099	25	30010	30010	30010	8522901	0	49	86999	0	90035	90080	85922	3	86265	30010	30020	60020	90035	176	2	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	1890	0	2	16	2	2	89751	30000	30010	90080	90036	90036	90036	90081
30024	90035	674	0	0	0	0	1	12	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	334	0	3	0	0	1890	0	2	16	2	2	89818	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	1023	0	726	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	3	0	0	1890	0	2	16	2	2	89813	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	1890	0	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	1890	0	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	2	3	0	0	1890	0	2	16	2	2	89751	30000	30010	90036	90067	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	49	86955	0	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	1890	0	2	24	2	2	89751	30000	30010	90036	90036	90036	90067	90036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0
  mov x2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	675	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	2	16	1	1	89751	30008	1	30100	90036	90036	90036	90036	90036
30204	90035	674	0	585	0	726	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30204	90035	674	0	285	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	2	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30204	90035	675	0	12	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	204	81120	25	30100	30100	30100	8522656	1	49	86955	3	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30204	90035	675	0	177	88	726	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30205	90035	675	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1910	1	16	1	1	89751	30000	0	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90035	674	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	4	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	3	0	1890	3	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	3	0	0	703	81210	25	30010	30010	30010	8522901	49	86955	90035	90074	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	5	50	3	3	89751	30000	30010	90036	90036	90036	90127	90214
30024	90035	674	0	1	0	0	12	0	726	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	21	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	2	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	89751	30008	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	1	1	0	0	82	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30123	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	4	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	61	81210	25	30019	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036

Test 4: throughput

Count: 8

Code:

  udiv x0, x8, x9
  udiv x1, x8, x9
  udiv x2, x8, x9
  udiv x3, x8, x9
  udiv x4, x8, x9
  udiv x5, x8, x9
  udiv x6, x8, x9
  udiv x7, x8, x9

Initialization

  mov x8, #0
  mov x9, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160038	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	1	5110	2	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5132	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	251	79950	25	80100	80100	80100	4399225	0	49	156958	160038	160038	149901	3	149996	80138	80200	160200	160038	261	2	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	160034	80000	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	1736	79950	38	80100	80100	80100	4399225	0	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80202	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	160038	160038	149901	3	149996	80100	80200	160328	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	94	79950	25	80100	80100	80100	4399225	0	49	156958	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160075

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	160038	1199	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	6	16	0	0	5	5	159980	80000	42	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	774	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	16	0	0	4	5	159980	80000	21	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	2	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	16	0	0	3	5	160165	80029	0	0	80010	160039	160039	160039	160039	160376
80024	160038	1198	0	3	1	0	0	0	768	79938	228	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80022	10	9	10	80010	10	0	1	0	0	0	0	5020	5	24	0	0	5	5	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	21	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	5020	5	16	0	0	5	5	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	16	0	0	6	6	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	6	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	16	0	0	7	7	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	528	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	16	0	0	5	4	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	16	0	0	7	6	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	84	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	16	0	0	5	5	159980	80000	0	0	80010	160039	160039	160039	160039	160039

UDIV (fast, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations