Firestorm: LDRB (register) measurements

Code:

  ldrb w0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	45	0	0	0	359	2	12	0	16	25	1000	1000	1000	15037	398	394	217	3	232	1000	1000	2000	374	77	1	1	1001	1000	1000	1	1000	0	1039	0	40	1039	6	0	39	43	73	2	16	2	2	391	10	10	4	1000	375	375	395	401	395
1004	394	3	0	0	45	0	0	0	359	0	12	12	16	25	1000	1000	1000	14060	394	398	197	3	256	1000	1000	2000	394	56	1	1	1001	1000	1000	1	1000	43	1039	0	39	1038	0	0	0	43	73	2	16	2	2	391	10	10	0	1000	399	375	375	395	395
1004	394	3	0	0	45	1	0	1	359	2	0	0	0	25	1000	1000	1000	15037	374	394	216	3	232	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	43	1039	0	39	1000	6	0	0	44	73	2	16	2	2	371	10	10	4	1000	375	375	399	399	399
1004	394	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15052	394	394	216	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1039	0	0	1039	6	1	0	43	73	2	16	2	2	391	10	0	0	1000	395	397	395	395	399
1004	394	3	0	0	45	0	0	1	359	2	1	12	19	25	1000	1000	1000	15353	394	394	197	3	252	1000	1000	2000	374	77	1	1	1001	1000	1000	0	1000	43	1000	0	39	1000	6	0	39	0	73	2	16	2	2	391	10	10	7	1000	395	378	395	375	375
1004	394	3	0	0	0	1	0	1	379	2	12	12	16	25	1000	1000	1000	14060	398	394	216	3	232	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1039	0	0	1000	6	1	39	0	73	2	16	2	2	391	0	10	4	1000	395	375	395	395	395
1004	394	2	0	0	45	1	0	1	359	0	1	1	19	25	1000	1000	1000	14203	374	374	217	3	252	1000	1000	2000	374	77	1	1	1001	1000	1000	1	1000	0	1039	0	39	1000	6	1	39	0	73	2	16	2	2	371	10	10	4	1000	395	375	399	400	395
1004	394	3	0	0	45	1	0	1	379	2	12	1	0	25	1000	1000	1000	14060	374	394	197	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	1	1000	43	1000	0	38	1039	6	1	0	43	73	2	16	2	2	371	10	10	0	1000	398	395	381	375	375
1004	394	3	0	0	0	0	0	1	379	2	12	12	16	25	1000	1000	1000	15182	374	398	197	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	0	1039	0	38	1039	0	1	0	0	73	2	16	2	1	395	10	10	0	1000	385	395	376	375	375
1004	374	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	14060	374	420	219	3	232	1000	1000	2000	374	56	1	1	1001	1000	1000	1	1000	43	1039	0	0	1039	0	1	0	43	73	2	16	2	2	391	10	14	5	1000	399	375	399	395	375

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	0	0	0	0	0	1	0	2	1	0	1	70042	69702	59716	25	40108	30106	10002	30100	10000	616068	3342542	0	49	67085	70061	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10000	1	0	54	10000	1	1	1	1	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70054	543	0	0	0	0	0	0	0	1	1	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	70125	70051	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	1	69814	30003	0	10	10	10000	30100	70052	70036	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40100	30103	10001	30100	10000	616014	3342254	1	49	66971	70054	70054	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	0	1	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70055	70055	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	543	0	0	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	70053	70054	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	0	0	1	0	4	0	0	2610	1	71	1	1	69814	30003	0	10	10	10000	30100	70172	70438	70151	70052	70052
40204	70051	524	0	0	0	0	1	0	0	1	1	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	67073	70053	70051	64631	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	1	69798	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	0	1	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	70051	70051	64647	0	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	1	69798	30003	10	10	10	10000	30100	70052	70052	70052	70052	70036
40204	70051	524	0	0	0	0	0	0	0	1	0	0	0	70036	69782	59710	39	40104	30100	10001	30100	10000	616014	3341470	1	49	66971	70051	70052	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	0	2610	1	71	1	1	69814	30003	0	10	10	10000	30100	70052	70052	70052	70093	70052
40204	70059	525	0	0	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	70055	70056	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70036	70036	70052	70052
40204	70051	524	0	0	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3341470	1	49	66971	70054	70051	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	1	69814	30003	10	0	10	10000	30100	70052	70052	70036	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	1	1	0	1	0	0	2	0	1	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	1	49	66973	70053	70114	64673	3	64978	40010	30683	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	2	1	10003	0	2	4708	10000	1	1	1	1	1	0	2520	2	71	3	4	69804	30006	0	6	6	10000	30010	70054	70054	70054	70042	70054
40024	70041	525	1	0	0	1	0	0	7	0	1	0	1	70026	69777	59712	25	40018	30016	10002	30010	10000	617009	3341769	1	49	66973	70053	70053	64671	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	0	10004	0	1	1	10000	0	1	1	1	1	0	2520	4	71	3	3	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70053	525	1	1	0	1	0	0	2	0	1	0	1	70026	69702	59712	25	40018	30016	10002	30010	10000	617009	3342350	1	49	66973	70053	70041	64671	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10002	0	1	1	10000	1	1	1	1	2	0	2521	3	71	3	2	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70053	525	1	0	0	0	0	0	2	0	1	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	1	49	66973	70053	70053	64671	3	64978	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10003	0	0	1	10000	1	1	1	1	2	0	2520	3	71	3	3	69804	30003	6	6	6	10000	30010	70054	70054	70042	70054	70054
40024	70041	525	1	1	0	0	0	0	2	0	0	0	1	70038	69777	59712	25	40014	30016	10002	30010	10000	617009	3342350	1	49	66961	70053	70053	64671	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	1	1	10002	0	1	1	10000	1	1	1	1	1	0	2520	3	71	3	3	69816	30006	0	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70053	525	1	1	0	0	0	0	2	0	1	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	1	49	66973	70053	70041	64671	3	64966	40010	30020	10219	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10004	2	1	10003	0	0	2397	10000	1	1	0	1	1	1	2520	3	71	2	2	69816	30006	6	6	6	10000	30010	70042	70054	70054	70042	70054
40024	70053	524	1	1	0	1	0	0	1	0	0	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	1	49	66973	70053	70053	64671	3	64978	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	0	1	10000	1	1	1	1	0	0	2522	2	71	2	2	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70042
40024	70041	524	1	1	0	0	0	0	2	0	1	0	1	70026	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	1	49	66961	70041	70053	64671	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	1	1	10000	1	1	1	1	1	0	2520	2	71	3	2	69804	30006	6	6	6	10000	30010	70042	70054	70042	70054	70054
40024	70041	525	1	1	0	1	0	0	1	0	0	0	1	70038	69777	59701	25	40018	30016	10002	30010	10000	616995	3342350	1	49	66973	70053	70053	64671	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	0	1	10000	1	1	1	1	2	0	2521	2	71	3	3	69816	30006	6	0	6	10000	30010	70054	70054	70042	70054	70054
40024	70053	525	1	1	0	1	0	0	2	0	0	0	1	70038	69777	59701	25	40018	30013	10001	30010	10000	617009	3342350	1	49	66973	70053	70053	64671	3	64978	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10001	0	1	1	10000	0	1	0	1	1	0	2520	2	71	4	4	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70054

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	0	0	0	0	0	0	10	0	1	0	70036	69785	59713	25	40100	30103	10002	30100	10000	616041	3341470	1	49	66974	70054	70035	64631	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	2	71	2	2	69817	30003	0	0	0	10000	30100	70055	70052	70055	70036	70055
40204	70054	525	0	0	0	1	1	0	1	0	1	0	70039	69785	59695	25	40104	30103	10001	30100	10000	616014	3343838	1	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	0	2610	2	71	2	2	69817	30003	13	13	0	10000	30100	70036	70055	70052	70036	70036
40204	70035	525	0	0	0	0	0	0	1	0	0	0	70039	69785	59695	25	40104	30103	10001	30100	10000	616014	3344926	1	49	66974	70035	70054	64650	3	64955	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	0	0	2610	2	71	3	2	69798	30000	13	10	13	10000	30100	70055	70036	70036	70052	70055
40204	70054	525	0	0	0	0	0	3	0	0	1	0	70036	69785	59713	25	40104	30103	10001	30100	10000	616770	3342494	1	49	66974	70035	70035	64647	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	9	10000	1	1	0	2610	2	71	2	2	69817	30003	13	10	13	10000	30100	70036	70036	70036	70055	70055
40204	70035	525	0	0	0	0	0	0	0	0	0	0	70039	69788	59715	25	40100	30103	10000	30100	10000	616014	3343838	1	49	66955	70035	70054	64650	3	64938	40100	30200	10000	60200	20000	70417	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	0	0	2610	2	71	2	2	69798	30003	13	13	10	10000	30100	70055	70055	70037	70056	70052
40204	70035	525	0	0	0	0	1	0	6	0	1	0	70020	69782	59695	25	40104	30103	10001	30100	10000	616014	3344462	1	49	66955	70051	70035	64700	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	1	0	2610	2	71	2	2	69798	30000	0	0	0	10000	30100	70055	70055	70055	70055	70055
40204	70035	525	0	0	0	0	0	0	0	0	0	0	70039	69764	59710	25	40104	30100	10000	30100	10000	616275	3342190	1	49	66955	70035	70054	64631	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	1	0	2610	2	71	2	2	69817	30003	13	13	0	10000	30100	70036	70036	70055	70055	70036
40204	70054	525	0	0	0	1	1	0	1	0	1	0	70039	69764	59713	25	40104	30100	10001	30100	10000	616014	3343150	1	49	66974	70051	70035	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	3	0	10000	1	0	0	2716	2	71	2	2	69817	30003	10	10	10	10000	30100	70055	70036	70052	70052	70052
40204	70054	525	0	0	0	1	1	0	1	0	1	0	70039	69764	59710	25	40100	30100	10001	30100	10000	616041	3344606	1	49	66974	70035	70035	64650	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	2	71	2	2	69817	30000	0	13	13	10000	30100	70036	70036	70055	70055	70036
40204	70054	525	0	0	0	1	0	0	1	0	1	0	70036	69785	59710	25	40104	30100	10001	30100	10000	616014	3345134	1	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	2	71	2	2	69817	30003	13	0	13	10000	30100	70036	70055	70055	70055	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	0	0	0	0	0	0	1	0	0	15	0	0	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	622382	3347726	1	0	49	66970	70050	70035	64665	3	64972	40010	30020	10000	61346	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	9142	10000	1	0	0	0	2520	5	3	5	71	7	5	69810	30000	6	6	6	10000	30010	70048	70036	70049	70051	70048
40024	70047	525	0	0	0	0	0	0	0	0	0	1	0	1	0	0	70020	69760	59695	25	40014	30045	10001	30010	10000	617009	3341470	1	5	49	66967	70035	70047	64653	3	65184	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	3	0	0	10000	1	0	0	2	2520	5	4	5	71	5	7	69810	30003	6	6	9	10000	30010	70048	70048	70036	70036	70048
40024	70050	527	1	0	0	0	0	0	0	0	0	13	0	1	0	0	70032	69743	59706	25	40014	30013	10001	30010	10000	619249	3343058	1	5	49	66970	70050	70035	64653	3	65196	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	2520	5	0	7	71	7	7	69810	30003	6	6	0	10000	30010	70037	70418	70039	70052	70048
40024	70047	524	1	0	0	0	0	0	0	0	2	1	0	1	0	0	70032	69743	59706	25	40014	30013	10001	30010	10000	617009	3342350	1	5	49	66967	70050	70047	64665	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	2520	5	4	7	71	7	5	69810	30003	9	9	9	10000	30010	70048	70048	70048	70048	70036
40024	70047	525	1	0	0	0	0	0	0	0	0	1	0	1	0	0	70032	69728	59706	25	40014	30013	10000	30010	10000	617009	3342350	1	5	49	66970	70047	70047	64668	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	2520	5	4	5	71	7	5	69810	30003	9	6	6	10000	30010	70051	70051	70048	70048	70048
40024	70047	524	1	0	0	0	0	0	0	0	0	1	0	0	0	0	70020	69760	59706	25	40014	30013	10001	30010	10000	617738	3342590	1	5	49	66970	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	2520	5	4	7	71	7	7	69810	30003	6	9	0	10000	30010	70038	70058	70048	70036	70036
40024	70047	525	1	0	0	0	0	1	1	0	0	0	0	0	0	0	70035	69760	59709	25	40014	30010	10001	30010	10000	617009	3342494	1	5	49	66967	70047	70050	64653	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	2520	5	4	5	71	7	5	69798	30000	6	0	9	10000	30010	70048	70048	70048	70051	70048
40024	70050	524	1	0	0	0	0	0	1	0	0	1	0	1	0	0	70035	69729	59695	25	40014	30013	10001	30010	10000	617486	3342686	1	5	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	2520	5	4	5	71	6	7	69798	30003	6	0	0	10000	30010	70036	70051	70048	70048	70036
40024	70047	525	0	2	0	0	0	0	0	0	0	52	352	1	0	0	70032	69743	59695	25	40010	30013	10001	30587	10000	617009	3342350	1	5	49	66970	70035	70035	64665	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	2520	5	4	7	71	8	7	69810	30003	0	9	9	10000	30010	70049	70418	70049	70051	70051
40024	70050	525	0	0	0	0	0	1	1	0	0	1	0	0	0	0	70032	69760	59709	25	40014	30010	10001	30010	10000	617009	3342350	1	5	49	66969	70233	70049	64665	3	64972	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	2520	5	4	5	71	7	5	69798	30003	9	9	9	10000	30010	70036	70048	70048	70048	70036

Test 4: throughput

Count: 8

Code:

  ldrb w0, [x6, x7]
  ldrb w0, [x6, x7]
  ldrb w0, [x6, x7]
  ldrb w0, [x6, x7]
  ldrb w0, [x6, x7]
  ldrb w0, [x6, x7]
  ldrb w0, [x6, x7]
  ldrb w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	1	66	0	1	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	1	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	1	100	80000	43	80039	0	0	39	80039	6	1	39	43	1	1	1	5118	1	16	0	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26729	200	1	1	0	45	0	1	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1181652	1	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80040	6	1	39	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	201	0	0	0	45	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1168636	1	49	23647	0	26727	26707	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	45	0	1	1	26712	2	12	12	16	25	80100	100	80000	100	80014	500	1173103	1	49	23647	0	26727	26707	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80040	6	1	0	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26728	26728	26728	26708	26728
80204	26727	200	0	0	0	45	0	1	1	26692	2	12	12	16	25	80100	100	80000	100	80015	500	1171316	1	49	23647	0	26727	26727	16635	6	16679	80116	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26729	26746	26728	26728	26728
80204	26727	200	1	1	0	45	0	0	1	26712	2	0	12	16	25	80100	100	80000	100	80014	500	1171993	1	49	23647	0	26707	26707	16833	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26747	26728	26728	26728	26708
80204	26707	200	0	0	0	45	0	1	1	26712	2	12	12	16	25	80100	100	80000	100	80014	500	1172581	1	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80039	6	1	40	43	1	1	1	5118	0	16	1	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	45	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80014	500	1171975	1	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80039	0	0	39	80039	6	0	39	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	45	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1181717	1	49	23653	0	26730	26727	16655	6	16659	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	45	0	0	1	26782	2	12	12	16	25	80100	100	80000	100	80015	500	1172418	1	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	0	0	45	1	0	1	26713	0	12	1	16	25	80010	10	80000	10	80000	50	1168843	0	49	23647	26731	26728	16672	3	16711	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80039	0	117	80038	6	1	39	43	0	5020	5	16	3	5	26728	10	10	4	80000	10	26728	26728	26729	26732	26732
80024	26829	200	0	0	0	1	0	1	26712	2	1	1	19	25	80010	10	80000	10	80000	50	1174273	0	49	23648	26731	26708	16672	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80000	0	128	80038	6	1	39	44	0	5020	2	16	4	2	26728	14	14	4	80000	10	26728	26732	26709	26729	26732
80024	26816	200	0	0	44	0	0	1	26712	2	1	12	19	25	80010	10	80000	10	80000	50	1167201	0	49	23651	26727	26727	16676	3	16711	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	38	80038	6	1	39	44	0	5020	2	16	4	3	26705	14	14	0	80000	10	26709	26732	26732	26729	26732
80024	26823	200	0	0	0	1	0	1	26716	2	1	1	16	25	80010	10	80000	10	80000	50	1157633	1	49	23647	26731	26728	16676	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	125	80038	6	1	39	44	0	5020	2	16	4	2	26727	10	10	4	80000	10	26728	26728	26728	26728	26709
80024	26825	200	0	0	44	1	0	1	26712	0	1	1	19	25	80010	10	80000	10	80000	50	1172344	0	49	23647	26731	26728	16672	3	16688	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80038	0	135	80038	6	1	39	44	0	5020	4	16	4	2	26705	10	10	7	80000	10	26728	26728	26728	26732	26732
80024	26853	200	0	0	45	1	0	1	26712	2	12	0	19	25	80010	10	80000	10	80000	50	1166468	0	49	23647	26728	26728	16672	3	16711	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	44	80000	0	119	80038	6	1	39	0	0	5020	2	16	4	3	26728	10	14	4	80000	10	26732	26709	26733	26732	26728
80024	26844	200	0	0	44	0	0	1	26713	2	0	1	16	25	80010	10	80000	10	80000	50	1168520	0	49	23651	26708	26708	16672	3	16708	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	131	80038	6	0	39	43	0	5020	2	16	2	4	26705	14	14	7	80000	10	26709	26732	26732	26732	26732
80024	26841	200	0	0	44	0	0	1	26693	2	0	12	16	25	80010	10	80000	10	80000	50	1167172	0	49	23651	26708	26727	16672	3	16707	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	39	80038	6	1	39	0	2	5020	4	16	4	2	26728	10	0	7	80000	10	26729	26732	26728	26732	26732
80024	26831	200	0	0	0	1	0	1	26716	2	1	1	19	25	80010	10	80000	10	80000	50	1169370	0	49	23647	26728	26727	16676	3	16711	80010	20	80000	20	160000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	140	80038	6	1	38	44	0	5020	4	16	4	4	26724	10	14	7	80000	10	26709	26732	26732	26729	26728
80024	26834	201	0	0	44	0	0	1	26713	2	1	1	19	25	80010	10	80000	10	80000	50	1162116	0	49	23651	26731	26731	16672	3	16708	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	129	80038	6	1	39	0	0	5020	4	16	2	4	26728	0	10	7	80000	10	26732	26729	26732	26709	26728

LDRB (register)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations