Firestorm: PRFM (register, PLDL1STRM) measurements

Code:

  prfm pldl1strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3a	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1576	12	32	16	31	0	2453	46	1608	891	25	1000	1000	1000	69879	1	1568	1592	1317	3	1465	1000	1000	1000	1605	1581	1	1	1001	257	2243	2243	3217	0	2423	2262	1000	73	1	16	1	1	1509	1000	1597	1597	1616	1628	1595
1004	1575	12	30	16	30	0	2438	18	1563	904	25	1000	1000	1000	70367	1	1611	1599	1314	3	1424	1000	1000	1000	1573	1575	1	1	1001	259	2242	2260	3246	0	2438	2229	1000	73	1	16	1	1	1498	1000	1638	1575	1577	1626	1587
1004	1595	12	32	17	32	0	2417	15	1602	925	25	1000	1000	1000	70308	0	1609	1597	1317	3	1452	1000	1000	1000	1586	1597	1	1	1001	227	2256	2262	3252	0	2434	2262	1000	73	1	16	1	1	1509	1000	1600	1599	1631	1630	1597
1004	1594	13	30	16	32	0	2435	44	1551	875	25	1000	1000	1000	69102	1	1616	1628	1311	3	1454	1000	1000	1000	1581	1594	1	1	1001	254	2241	2263	3262	0	2425	2253	1000	73	1	16	1	1	1549	1000	1572	1581	1599	1613	1736
1004	1606	12	32	16	30	0	2435	9	1604	900	54	1000	1000	1000	69432	1	1558	1572	1320	3	1438	1000	1000	1000	1577	1617	1	1	1001	251	2268	2256	3270	0	2423	2254	1000	92	1	16	1	1	1507	1000	1573	1595	1626	1637	1640
1004	1566	12	30	15	33	0	2439	19	1625	880	25	1000	1000	1000	68819	0	1585	1606	1318	3	1482	1000	1000	1000	1620	1594	1	1	1001	262	2253	2246	3250	0	2419	2250	1000	73	1	16	1	1	1508	1000	1627	1627	1632	1611	1600
1004	1630	13	32	16	30	0	2454	50	1615	881	25	1000	1000	1000	68989	1	1577	1575	1323	3	1458	1000	1000	1000	1580	1602	1	1	1001	265	2236	2247	3248	0	2430	2256	1000	73	1	16	1	1	1513	1000	1630	1632	1626	1628	1581
1004	1600	12	31	17	32	0	2425	51	1603	896	25	1000	1000	1000	67920	1	1568	1607	1317	3	1431	1000	1000	1000	1595	1565	1	1	1001	287	2262	2235	3243	0	2429	2247	1000	73	1	16	1	1	1500	1000	1637	1598	1613	1626	1631
1004	1580	12	33	15	30	0	2395	19	1609	888	25	1000	1000	1000	69745	0	1588	1627	1312	3	1447	1000	1000	1000	1594	1605	1	1	1001	245	2275	2294	3253	0	2453	2250	1000	73	1	16	1	1	1505	1000	1583	1574	1624	1581	1628
1004	1639	12	30	16	32	1	2437	54	1582	867	25	1000	1000	1000	68315	0	1572	1629	1297	3	1487	1000	1000	1000	1562	1606	1	1	1001	251	2244	2254	3268	0	2424	2235	1000	73	1	16	1	1	1495	1000	1611	1558	1598	1590	1630

Test 2: throughput

Code:

  prfm pldl1strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5868

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15971	118	327	178	327	0	0	24397	0	10376	15743	9977	25	20222	10199	10000	10108	10000	134472	741653	0	43	49	12645	15769	15789	13115	6	13376	20125	10208	10008	10212	10004	15806	159	1	1	20201	100	99	2414	100	10100	100	22556	22635	32613	0	0	0	24236	22473	10000	0	1	1	1	1319	0	16	0	0	15747	10123	10000	10100	15800	15731	15872	15739	15895
20204	15743	120	333	175	331	0	0	24361	0	10422	15746	9911	25	20223	10211	10000	10104	10005	133232	737686	0	34	49	12791	15763	15862	13146	6	13279	20104	10212	10020	10204	10012	15841	154	1	1	20201	100	99	2559	100	10100	100	22595	22633	32643	0	0	0	24615	22451	10000	0	1	1	1	1318	0	16	0	0	15573	10090	10000	10100	15854	15856	15786	15857	15671
20204	15838	120	331	181	336	0	0	24242	0	10387	15857	9852	25	20214	10199	10000	10100	10000	132227	740239	0	41	49	12821	15723	16062	13116	3	13323	20100	10200	10000	10200	10000	15898	158	1	1	20201	100	99	2650	100	10100	100	22625	22547	32546	0	0	0	24182	22528	10000	0	0	0	0	1310	1	17	1	1	15750	10138	10000	10100	15761	15860	15792	15879	15788
20204	15803	119	327	178	332	0	0	24340	0	7243	15725	9951	25	20190	10220	10000	10100	10000	133653	744177	0	38	49	12720	15699	15768	13187	3	13209	20100	10200	10000	10200	10000	15816	156	1	1	20201	100	99	2457	100	10100	100	22640	22642	32601	0	0	0	24176	22587	10000	0	0	0	0	1310	1	16	1	1	15747	10129	10000	10100	15901	15975	15875	15898	15814
20204	15884	119	325	178	327	0	0	24276	0	7293	15844	9810	25	20229	10199	10000	10100	10000	132608	747796	0	38	49	12708	15808	15759	13127	3	13147	20100	10200	10000	10200	10000	15669	157	2	1	20201	100	99	2522	100	10100	100	22665	22644	32628	0	0	0	24216	22599	10000	0	0	0	0	1310	1	16	1	1	15599	10108	10000	10100	15738	15899	15714	15786	15916
20204	15943	119	342	181	326	0	0	24378	0	7246	15775	9783	25	20223	10226	10000	10100	10000	133691	738518	0	35	49	12910	15953	15822	13131	3	13333	20100	10200	10000	10200	10000	15987	157	2	1	20201	100	99	2493	100	10100	100	22631	22662	32541	0	0	0	24198	22548	10000	0	0	0	0	1310	1	16	1	1	15687	10099	10000	10100	15809	15773	15842	15892	15818
20204	15822	120	329	184	331	0	0	24162	0	7289	15803	9752	25	20220	10193	10000	10100	10000	133237	747008	0	40	49	12779	15827	15851	12973	3	13334	20100	10200	10000	10200	10000	15796	159	1	1	20201	100	99	2564	100	10100	100	22564	22510	32473	0	0	0	24270	22660	10000	0	0	0	0	1310	1	16	1	1	15632	10099	10000	10100	15774	15784	15891	15923	15776
20204	15912	118	330	175	336	0	0	24263	0	7285	15744	9947	25	20193	10208	10000	10100	10000	134914	743109	0	36	49	12711	15851	15767	13060	3	13306	20100	10200	10000	10200	10000	15890	154	1	1	20201	100	99	2640	100	10100	100	22658	22570	32550	0	0	0	24287	22443	10000	0	0	0	0	1310	1	16	1	1	15656	10096	10000	10100	15932	15854	15886	15828	15790
20204	15905	119	330	178	336	0	0	24299	0	7305	15812	9886	25	20193	10217	10000	10100	10000	133895	735125	0	33	49	12805	15933	15916	13177	3	13294	20100	10200	10000	10200	10000	15717	158	1	1	20201	100	99	2511	100	10100	100	22610	22558	32545	0	0	0	24661	22647	10000	0	0	0	0	1311	1	16	1	1	15645	10126	10000	10100	15839	15942	15780	15782	15939
20204	15935	119	326	178	333	0	0	24258	0	7309	15809	9893	25	20232	10229	10000	10100	10000	135361	742608	0	35	49	12816	15823	15891	13088	3	13206	20100	10200	10000	10200	10000	15740	157	1	1	20201	100	99	2543	100	10100	100	22568	22559	32691	0	0	0	24262	22543	10000	0	0	0	0	1310	1	16	1	1	15734	10111	10000	10100	15907	15718	15858	15832	15943

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5651

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15669	117	361	194	358	24602	10513	15549	9657	25	20145	10169	10000	10010	10000	129818	732405	1	51	49	12581	15711	15654	12936	3	13205	20010	10020	10000	10020	10000	15580	154	1	1	20021	10	9	2289	10	10010	10	22836	22941	32913	0	0	0	24524	23024	10000	0	1270	1	16	1	1	15589	10147	10000	10010	15622	15529	15596	15631	15650
20024	15625	118	359	195	363	24515	10507	15686	9615	25	20130	10148	10000	10010	10000	131089	734418	0	35	49	12624	15648	15635	13034	3	13081	20010	10020	10000	10020	10000	15544	154	1	1	20021	10	9	2212	10	10010	10	22775	22810	32871	0	0	0	24613	22834	10000	0	1270	1	16	1	1	15553	10147	10000	10010	15583	15720	15621	15672	15724
20024	15591	118	357	187	359	24564	10628	15563	9640	25	20166	10154	10000	10010	10000	131119	730307	1	50	49	12560	15689	15639	13016	3	13060	20010	10020	10000	10020	10000	15570	157	1	1	20021	10	9	2325	10	10010	10	22922	22944	32906	0	0	0	24779	22987	10000	0	1270	1	16	1	1	15395	10138	10000	10010	15758	15622	15704	15691	15565
20024	15685	116	356	183	357	24589	10527	15611	9789	25	20163	10127	10000	10010	10000	131308	731990	1	51	49	12588	15679	15602	12954	3	13225	20010	10020	10000	10020	10000	15561	154	1	1	20021	10	9	2209	10	10010	10	22850	22850	32938	0	0	0	24832	22903	10000	0	1270	1	16	1	1	15481	10159	10000	10010	15745	15653	15714	15675	15670
20024	15652	117	357	188	357	24492	10500	15591	9696	25	20145	10175	10000	10010	10000	131086	733711	1	40	49	12643	15610	15589	12887	3	13018	20010	10020	10000	10020	10000	15631	154	1	1	20021	10	9	2223	10	10010	10	22862	22904	32943	0	0	0	24625	22993	10000	0	1270	1	16	1	1	15538	10138	10000	10010	15701	15625	15714	15727	15604
20024	15707	116	362	189	362	24606	10565	15684	9719	25	20166	10136	10000	10010	10000	130769	729550	1	35	49	12640	15696	15661	12960	3	13048	20010	10020	10000	10020	10000	15649	154	1	1	20021	10	9	2278	10	10010	10	22999	23051	32814	0	0	0	24729	23088	10000	0	1271	1	16	1	1	15570	10135	10000	10010	15646	15789	15548	15730	15594
20024	15651	121	359	187	357	24614	10524	15608	9744	25	20145	10118	10000	10010	10000	130761	729235	1	50	49	12620	15567	15534	12990	3	13057	20010	10020	10000	10020	10000	15604	156	1	1	20021	10	9	2300	10	10010	10	23013	23143	32832	0	0	0	24466	23045	10000	0	1270	1	16	1	3	15523	10138	10000	10010	15856	15696	15572	15647	15697
20024	15625	117	358	194	362	24502	10553	15589	9665	25	20148	10145	10000	10010	10000	132202	730928	1	52	49	12579	15744	15652	12968	3	13146	20010	10020	10000	10020	10000	15589	154	1	1	20021	10	9	2359	10	10010	10	22796	22906	33035	0	0	0	24748	22865	10000	0	1270	1	16	1	1	15445	10132	10000	10010	15692	15484	15655	15722	15676
20024	15484	117	358	194	361	24918	10530	15702	9794	25	20136	10118	10000	10010	10000	130730	730143	1	47	49	12499	15686	15601	12967	3	13164	20010	10020	10000	10020	10000	15642	155	1	1	20021	10	9	2246	10	10010	10	22827	22892	32943	0	0	0	24731	22750	10000	0	1270	1	16	1	1	15477	10144	10000	10010	15610	15694	15581	15655	15585
20024	15526	117	357	190	362	24644	10638	15523	9808	25	20139	10127	10000	10010	10000	131077	739363	1	42	49	12613	15623	15611	12800	3	13093	20010	10020	10000	10020	10000	15612	156	1	1	20021	10	9	2362	10	10010	10	22921	22828	33015	0	0	0	24540	22876	10000	0	1270	1	16	1	1	15496	10147	10000	10010	15528	15687	15631	15665	15690

Test 3: throughput

Code:

  prfm pldl1strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5475

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15520	116	290	146	289	23879	0	137	15519	9498	25	10100	100	10000	100	10000	500	724405	0	49	12376	0	15479	15467	14050	7	14179	10100	200	10008	200	10016	15431	12226	1	1	10201	100	99	2652	100	100	100	22143	22231	32237	0	0	23892	22199	10000	1	1	1	719	0	16	0	0	15384	0	10000	100	15549	15504	15560	15634	15578
10204	15495	116	290	145	296	23865	0	131	15477	9544	25	10100	100	10000	100	10000	500	728831	0	49	12378	0	15452	15527	14143	7	14251	10103	200	10016	200	10016	15495	12189	1	1	10201	100	99	2679	100	100	100	22103	22139	32212	0	0	23904	22166	10000	1	1	1	718	0	16	0	0	15454	0	10000	100	15456	15470	15431	15515	15422
10204	15465	116	289	146	289	23904	0	517	15500	9602	25	10100	100	10000	100	10000	500	724818	1	49	12342	0	15528	15457	14083	6	14174	10103	200	10016	200	10008	15502	12256	1	1	10201	100	99	2555	100	100	100	22192	22279	32189	0	0	23874	22237	10000	1	1	1	717	0	16	0	0	15346	0	10000	100	15533	15458	15485	15480	15455
10204	15471	117	288	145	287	23852	0	119	15471	9569	25	10100	100	10000	100	10000	500	729277	1	49	12422	0	15454	15509	14022	7	14137	10100	200	10016	200	10016	15443	12250	1	1	10201	100	99	2655	100	100	100	22237	22212	32199	0	0	23924	22279	10000	1	1	1	717	0	16	0	0	15411	0	10000	100	15531	15503	15568	15478	15534
10204	15469	116	292	146	292	23901	0	132	15486	9535	25	10100	100	10000	100	10000	500	722922	1	49	12353	0	15471	15480	13987	7	14207	10100	200	10008	200	10016	15491	12198	1	1	10201	100	99	2613	100	100	100	22143	22231	32198	0	0	23892	22125	10000	1	1	1	718	0	16	0	0	15396	0	10000	100	15471	15605	15532	15472	15466
10204	15560	116	286	145	288	23908	0	517	15442	9504	25	10100	100	10000	100	10002	500	724233	1	49	12306	0	15480	15499	14110	6	14162	10100	200	10024	200	10008	15463	12153	1	1	10201	100	99	2549	100	100	100	22271	22235	32165	0	0	23934	22177	10000	1	1	1	718	0	16	0	0	15312	0	10000	100	15468	15488	15513	15493	15470
10204	15490	117	291	146	289	23919	0	144	15565	9582	25	10100	100	10000	100	10001	500	722400	1	49	12381	0	15410	15428	14001	7	14189	10100	200	10008	200	10008	15417	12238	1	1	10201	100	99	2614	100	100	100	22103	22217	32182	0	0	23884	22145	10000	1	1	1	717	0	16	0	0	15409	0	10000	100	15771	15587	15493	15515	15502
10204	15420	117	289	144	290	23875	0	123	15478	9552	25	10100	100	10000	100	10000	500	722481	1	49	12464	0	15539	15513	14083	6	14138	10100	200	10016	200	10008	15476	12272	1	1	10201	100	99	2717	100	100	100	22169	22227	32176	0	0	23958	22189	10000	1	1	1	719	0	16	0	0	15405	0	10000	100	15563	15400	15508	15500	15485
10204	15462	116	293	142	293	23910	0	128	15540	9577	25	10100	100	10000	100	10006	500	723980	1	49	12509	0	15509	15507	13999	7	14144	10100	200	10016	200	10008	15513	12266	1	1	10201	100	99	2575	100	100	100	22207	22152	32282	0	0	23896	22255	10000	1	1	1	717	0	16	0	0	15363	0	10000	100	15431	15533	15556	15456	15465
10204	15431	116	292	145	289	23882	0	135	15520	9507	25	10100	100	10000	100	10002	500	721626	1	49	12448	0	15457	15455	14063	6	14271	10102	200	10016	200	10016	15470	12269	1	1	10201	100	99	2650	100	100	100	22256	22243	32241	0	0	23960	22193	10000	1	1	1	717	0	16	0	0	15353	0	10000	100	15518	15465	15566	15469	15494

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5481

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15484	116	289	144	291	0	23954	504	15448	9576	25	10010	10	10000	10	10000	50	725752	49	12472	15491	15422	14002	3	14164	10010	20	10000	20	10000	15394	15487	1	1	10021	10	9	2560	10	10	10	22228	22194	32160	1	23874	22135	10000	640	3	16	3	2	15346	10000	10	15511	15487	15498	15581	15562
10024	15552	116	289	146	290	0	23927	516	15477	9488	25	10010	10	10000	10	10000	50	724508	49	12388	15479	15547	14081	3	14234	10010	20	10000	20	10000	15437	15407	1	1	10021	10	9	2582	10	10	10	22174	22162	32143	0	23927	22176	10000	640	2	16	3	2	15258	10000	10	15456	15505	15668	15456	15552
10024	15459	116	284	145	288	0	23918	517	15492	9557	25	10010	10	10000	10	10000	50	726973	49	12404	15473	15427	14068	3	14266	10010	20	10000	20	10000	15470	15447	1	1	10021	10	9	2631	10	10	10	22137	22223	32227	0	23868	22227	10000	640	2	16	3	2	15392	10000	10	15586	15509	15522	15491	15428
10024	15510	116	293	145	294	0	24024	498	15486	9559	25	10010	10	10000	10	10000	50	726038	49	12382	15530	15485	14025	3	14257	10010	20	10000	20	10000	15437	15438	1	1	10021	10	9	2601	10	10	10	22242	22143	32160	0	23968	22213	10000	640	2	16	2	2	15388	10000	10	15491	15846	15493	15530	15540
10024	15522	115	291	147	291	1	23839	521	15528	9548	25	10010	10	10000	10	10000	50	727694	49	12421	15471	15523	14040	3	14216	10010	20	10000	20	10000	15458	15379	1	1	10021	10	9	2647	10	10	10	22192	22261	32184	0	23979	22166	10000	640	2	16	2	2	15327	10000	10	15473	15536	15532	15481	15420
10024	15425	115	292	145	294	0	23844	513	15477	9580	25	10010	10	10000	10	10000	50	726708	49	12389	15479	15491	14104	3	14154	10010	20	10000	20	10000	15436	15393	1	1	10021	10	9	2572	10	10	10	22142	22225	32193	0	23951	22058	10000	640	2	16	3	2	15327	10000	10	15418	15521	15514	15466	15524
10024	15526	116	286	144	288	0	23976	519	15538	9562	25	10010	10	10000	10	10000	50	722403	49	12436	15461	15495	14017	3	14286	10010	20	10000	20	10000	15499	15454	1	1	10021	10	9	2646	10	10	10	22167	22202	32184	0	23917	22162	10000	640	2	16	2	2	15370	10000	10	15537	15436	15550	15454	15543
10024	15470	116	289	147	290	0	23864	137	15460	9536	25	10010	10	10000	10	10000	50	723451	49	12397	15485	15464	14046	3	14283	10010	20	10000	20	10000	15389	15434	1	1	10021	10	9	2590	10	10	10	22267	22178	32192	0	23939	22204	10000	640	2	16	3	2	15400	10000	10	15524	15556	15541	15499	15529
10024	15422	116	289	146	291	0	23977	517	15474	9544	25	10010	10	10000	10	10000	50	722488	49	12412	15449	15437	14078	3	14252	10010	20	10000	20	10000	15462	15483	1	1	10021	10	9	2614	10	10	10	22114	22183	32171	0	23876	22180	10000	640	2	16	3	2	15356	10000	10	15530	15509	15473	15496	15485
10024	15577	116	291	145	294	0	23980	124	15444	9472	25	10010	10	10000	10	10000	50	724089	49	12436	15511	15495	14009	3	14279	10010	20	10000	20	10000	15484	15421	1	1	10021	10	9	2571	10	10	10	22162	22203	32218	0	23931	22147	10000	640	2	16	2	2	15397	10000	10	15485	15482	15524	15552	15484

PRFM (register, PLDL1STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations