Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stp w0, w1, [x6], #8
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 7 | 0 | 0 | 0 | 9 | 5 | 34 | 1 | 0 | 19 | 0 | 1025 | 20 | 9 | 9 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50746 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 109 | 0 | 0 | 1005 | 0 | 0 | 0 | 5 | 1005 | 6 | 88 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 13 | 0 | 1025 | 25 | 33 | 28 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1030 | 0 | 109 | 4 | 18 | 1005 | 1 | 30 | 20 | 11 | 1035 | 7 | 108 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 0 | 16 | 28 | 0 | 0 | 12 | 12 | 1025 | 7 | 5 | 8 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 93 | 0 | 0 | 1005 | 1 | 32 | 0 | 31 | 1032 | 5 | 76 | 73 | 3 | 17 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 0 | 15 | 26 | 1 | 0 | 17 | 0 | 1025 | 20 | 26 | 8 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1028 | 0 | 86 | 8 | 23 | 1008 | 0 | 18 | 12 | 26 | 1025 | 5 | 88 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 15 | 0 | 1025 | 15 | 36 | 31 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50746 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1028 | 0 | 109 | 3 | 18 | 1005 | 3 | 0 | 20 | 11 | 1037 | 5 | 96 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 6 | 11 | 0 | 0 | 0 | 12 | 0 | 1025 | 23 | 5 | 35 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1022 | 0 | 73 | 10 | 22 | 1007 | 1 | 22 | 14 | 16 | 1031 | 5 | 89 | 73 | 4 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 9 | 0 | 0 | 0 | 6 | 9 | 21 | 0 | 0 | 11 | 20 | 1025 | 15 | 9 | 44 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 0 | 105 | 8 | 22 | 1008 | 1 | 30 | 0 | 8 | 1005 | 5 | 96 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 14 | 0 | 1025 | 19 | 36 | 41 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 69 | 0 | 0 | 1005 | 0 | 0 | 0 | 5 | 1005 | 5 | 80 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 0 | 33 | 10 | 0 | 0 | 0 | 11 | 12 | 1025 | 27 | 24 | 5 | 7 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 109 | 0 | 0 | 1005 | 0 | 0 | 0 | 5 | 1005 | 5 | 72 | 73 | 3 | 17 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 0 | 0 | 10 | 27 | 1 | 24 | 12 | 4 | 1025 | 0 | 5 | 3 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1031 | 0 | 101 | 3 | 0 | 1011 | 5 | 0 | 14 | 8 | 1005 | 5 | 104 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
stp w0, w1, [x6], #8
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10209 | 10040 | 75 | 1 | 0 | 1 | 0 | 2244 | 88 | 823 | 1 | 776 | 83 | 0 | 120 | 10025 | 768 | 117 | 106 | 12 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 522183 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8681 | 6 | 8743 | 20106 | 200 | 10008 | 200 | 30024 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10905 | 7 | 1195 | 337 | 0 | 693 | 10262 | 260 | 1 | 904 | 36 | 805 | 10938 | 12 | 1076 | 0 | 0 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 1 | 0 | 0 | 2163 | 98 | 813 | 1 | 680 | 69 | 4 | 116 | 10025 | 775 | 149 | 123 | 34 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522101 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10922 | 0 | 1303 | 357 | 0 | 658 | 10262 | 257 | 0 | 916 | 32 | 789 | 10947 | 8 | 1174 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 0 | 2307 | 81 | 823 | 1 | 672 | 90 | 0 | 156 | 10025 | 794 | 96 | 104 | 23 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522101 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8675 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10954 | 8 | 1444 | 367 | 0 | 679 | 10236 | 259 | 0 | 918 | 40 | 841 | 10908 | 16 | 1206 | 7 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 1 | 0 | 0 | 1815 | 85 | 868 | 1 | 760 | 75 | 0 | 116 | 10025 | 807 | 105 | 107 | 21 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522163 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10929 | 8 | 1383 | 378 | 0 | 694 | 10256 | 280 | 1 | 906 | 32 | 769 | 10916 | 17 | 1189 | 7 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 76 | 1 | 1 | 1 | 0 | 2100 | 85 | 851 | 1 | 744 | 80 | 0 | 168 | 10025 | 794 | 89 | 114 | 33 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522165 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10886 | 0 | 1406 | 372 | 0 | 673 | 10262 | 289 | 0 | 886 | 46 | 850 | 10932 | 10 | 1031 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 0 | 0 | 2157 | 90 | 802 | 1 | 760 | 79 | 0 | 156 | 10025 | 790 | 109 | 117 | 26 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522141 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10890 | 0 | 1359 | 370 | 0 | 682 | 10242 | 286 | 0 | 898 | 46 | 841 | 10911 | 10 | 1222 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 1 | 1 | 0 | 2250 | 102 | 805 | 1 | 760 | 87 | 0 | 156 | 10025 | 779 | 96 | 99 | 23 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522187 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10930 | 0 | 1354 | 376 | 0 | 686 | 10249 | 267 | 0 | 906 | 42 | 861 | 10911 | 7 | 1069 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 2 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 1 | 0 | 0 | 2058 | 87 | 841 | 1 | 736 | 73 | 0 | 104 | 10025 | 797 | 99 | 96 | 28 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522117 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10912 | 0 | 1293 | 387 | 0 | 663 | 10264 | 263 | 0 | 940 | 38 | 853 | 10893 | 9 | 1141 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 1 | 0 | 2049 | 83 | 789 | 1 | 752 | 67 | 0 | 156 | 10025 | 802 | 110 | 90 | 22 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522187 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10920 | 0 | 1313 | 370 | 0 | 686 | 10233 | 281 | 0 | 886 | 36 | 825 | 10936 | 8 | 1153 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 1 | 1 | 0 | 2070 | 99 | 827 | 1 | 728 | 80 | 0 | 120 | 10025 | 814 | 120 | 106 | 40 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522133 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10908 | 0 | 1340 | 382 | 0 | 679 | 10248 | 259 | 0 | 924 | 36 | 877 | 10900 | 6 | 1199 | 0 | 0 | 0 | 0 | 0 | 737 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10029 | 10040 | 75 | 1 | 1 | 1 | 0 | 2073 | 96 | 818 | 2 | 512 | 89 | 0 | 276 | 10025 | 776 | 0 | 147 | 171 | 36 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521097 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10921 | 7 | 1452 | 392 | 0 | 674 | 10228 | 261 | 2 | 948 | 94 | 871 | 10919 | 29 | 1320 | 7 | 2 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 0 | 2187 | 103 | 879 | 2 | 488 | 81 | 0 | 260 | 10025 | 797 | 0 | 173 | 160 | 52 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521041 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10937 | 7 | 1309 | 385 | 0 | 674 | 10269 | 283 | 1 | 930 | 70 | 867 | 10976 | 24 | 1280 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 2103 | 84 | 832 | 2 | 544 | 87 | 1 | 188 | 10025 | 788 | 0 | 141 | 157 | 33 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521089 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10916 | 7 | 1442 | 375 | 0 | 672 | 10240 | 272 | 1 | 899 | 78 | 853 | 10860 | 21 | 1264 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 0 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 2016 | 81 | 809 | 2 | 584 | 84 | 0 | 252 | 10025 | 843 | 0 | 193 | 190 | 43 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521017 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10875 | 7 | 1427 | 409 | 0 | 672 | 10268 | 273 | 0 | 882 | 76 | 919 | 10945 | 26 | 1308 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 3 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 1 | 0 | 2109 | 101 | 845 | 2 | 560 | 82 | 0 | 312 | 10025 | 783 | 0 | 171 | 117 | 44 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521081 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10913 | 7 | 1485 | 357 | 0 | 718 | 10245 | 279 | 0 | 886 | 74 | 824 | 10955 | 20 | 1242 | 7 | 0 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 3 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 1 | 2202 | 101 | 825 | 2 | 568 | 85 | 0 | 292 | 10025 | 794 | 0 | 147 | 197 | 52 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521065 | 468824 | 1 | 49 | 6960 | 10040 | 10099 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10900 | 8 | 1346 | 372 | 0 | 714 | 10255 | 271 | 0 | 930 | 90 | 851 | 10908 | 30 | 1323 | 7 | 0 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 1 | 1 | 2316 | 89 | 833 | 2 | 528 | 89 | 0 | 244 | 10025 | 783 | 0 | 161 | 180 | 44 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521097 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10925 | 8 | 1360 | 350 | 0 | 686 | 10247 | 291 | 0 | 906 | 96 | 875 | 10922 | 22 | 1330 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 0 | 2043 | 97 | 827 | 2 | 504 | 85 | 1 | 236 | 10025 | 826 | 0 | 168 | 157 | 45 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521009 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10891 | 7 | 1405 | 393 | 0 | 696 | 10252 | 282 | 0 | 908 | 122 | 877 | 10892 | 20 | 1195 | 7 | 0 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 7 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 1 | 0 | 2022 | 84 | 866 | 2 | 600 | 96 | 0 | 252 | 10025 | 806 | 0 | 184 | 163 | 47 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10914 | 8 | 1381 | 402 | 0 | 666 | 10238 | 256 | 0 | 918 | 82 | 850 | 10916 | 27 | 1365 | 7 | 0 | 640 | 3 | 16 | 3 | 2 | 10037 | 10000 | 0 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 2091 | 93 | 849 | 2 | 552 | 89 | 3 | 240 | 10025 | 826 | 0 | 209 | 179 | 38 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521105 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10089 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10943 | 7 | 1461 | 405 | 0 | 712 | 10232 | 254 | 1 | 894 | 86 | 843 | 10910 | 18 | 1273 | 7 | 2 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
stp w0, w1, [x6], #8 stp w0, w1, [x7], #8 stp w0, w1, [x8], #8 stp w0, w1, [x9], #8 stp w0, w1, [x10], #8 stp w0, w1, [x11], #8 stp w0, w1, [x12], #8 stp w0, w1, [x13], #8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5098
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80209 | 40648 | 305 | 0 | 0 | 1680 | 841 | 768 | 1 | 712 | 118 | 172 | 40746 | 768 | 1564 | 1720 | 173 | 25 | 160759 | 83737 | 80000 | 80114 | 80008 | 403183 | 1873036 | 0 | 278 | 49 | 37666 | 40829 | 40793 | 30676 | 6 | 30750 | 160122 | 200 | 80016 | 200 | 240048 | 40792 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80874 | 0 | 4260 | 515 | 14 | 902 | 80507 | 236 | 880 | 36 | 1572 | 81505 | 525 | 3603 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40929 | 80763 | 80000 | 80100 | 40723 | 40736 | 40727 | 40811 | 40844 |
| 80204 | 40727 | 306 | 0 | 0 | 1809 | 842 | 790 | 1 | 680 | 109 | 116 | 40776 | 783 | 1545 | 1990 | 200 | 67 | 160415 | 82920 | 80000 | 80114 | 80008 | 402619 | 1872172 | 0 | 1765 | 49 | 37638 | 40741 | 40783 | 30594 | 6 | 30828 | 160123 | 202 | 80016 | 200 | 240048 | 40808 | 81 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80889 | 0 | 3838 | 470 | 9 | 861 | 80516 | 257 | 899 | 42 | 3228 | 81361 | 491 | 4457 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40784 | 83358 | 80000 | 80100 | 40672 | 40836 | 40780 | 40769 | 40764 |
| 80204 | 40821 | 306 | 0 | 0 | 1782 | 887 | 794 | 1 | 728 | 128 | 100 | 40790 | 778 | 1736 | 1787 | 138 | 25 | 165233 | 80672 | 80004 | 80116 | 80008 | 406305 | 1890016 | 0 | 719 | 49 | 38053 | 40744 | 40810 | 30801 | 6 | 30704 | 160123 | 200 | 80016 | 200 | 240048 | 40868 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80847 | 0 | 3666 | 456 | 14 | 890 | 80524 | 246 | 883 | 26 | 2997 | 81397 | 519 | 3701 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40721 | 88235 | 80000 | 80100 | 40823 | 40801 | 40811 | 40748 | 40720 |
| 80204 | 40873 | 305 | 0 | 0 | 2049 | 897 | 726 | 1 | 680 | 115 | 144 | 40824 | 770 | 1802 | 1690 | 140 | 25 | 160731 | 80645 | 80000 | 80114 | 80005 | 403180 | 1874842 | 0 | 1256 | 49 | 37707 | 40740 | 40867 | 30920 | 6 | 30786 | 160123 | 200 | 80000 | 200 | 240000 | 40779 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80907 | 0 | 4141 | 461 | 11 | 867 | 80522 | 245 | 856 | 108 | 1618 | 81375 | 479 | 4025 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40758 | 82520 | 80000 | 80100 | 40888 | 40738 | 40729 | 40811 | 40803 |
| 80204 | 40714 | 305 | 2 | 0 | 1791 | 831 | 789 | 1 | 720 | 115 | 116 | 40776 | 779 | 1504 | 1719 | 145 | 25 | 161658 | 81172 | 80073 | 80100 | 80000 | 402548 | 1874008 | 0 | 2379 | 49 | 37668 | 40773 | 40645 | 30703 | 3 | 30796 | 160100 | 200 | 80000 | 200 | 240000 | 40754 | 82 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80862 | 0 | 3948 | 469 | 10 | 839 | 80514 | 231 | 834 | 38 | 1619 | 81446 | 493 | 3589 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40781 | 80509 | 80000 | 80100 | 40776 | 40763 | 40759 | 40734 | 40756 |
| 80204 | 40717 | 304 | 0 | 0 | 1728 | 938 | 770 | 1 | 712 | 137 | 128 | 40776 | 791 | 1930 | 1962 | 90 | 25 | 160714 | 80908 | 80000 | 80100 | 80000 | 402359 | 1875136 | 0 | 237 | 49 | 37733 | 40750 | 40757 | 30727 | 3 | 30813 | 160100 | 200 | 80000 | 200 | 240000 | 40735 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80855 | 0 | 4036 | 462 | 2 | 880 | 80524 | 264 | 888 | 44 | 1431 | 81450 | 525 | 3940 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40728 | 80383 | 80000 | 80100 | 40773 | 40748 | 40823 | 40805 | 40717 |
| 80204 | 40825 | 305 | 0 | 0 | 1899 | 793 | 781 | 1 | 680 | 132 | 124 | 40656 | 769 | 2060 | 1761 | 132 | 25 | 160565 | 80819 | 80000 | 80100 | 80000 | 402311 | 1875448 | 0 | 1390 | 49 | 37762 | 40735 | 40810 | 30760 | 3 | 30670 | 160100 | 200 | 80000 | 200 | 240000 | 40783 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80868 | 0 | 4256 | 474 | 21 | 831 | 80560 | 235 | 866 | 52 | 1497 | 81415 | 535 | 3593 | 0 | 0 | 0 | 5110 | 0 | 17 | 1 | 1 | 40873 | 86577 | 80000 | 80100 | 40793 | 40872 | 40781 | 40755 | 40834 |
| 80204 | 40728 | 306 | 0 | 0 | 1524 | 760 | 785 | 1 | 696 | 116 | 132 | 40725 | 766 | 1753 | 1758 | 73 | 25 | 161030 | 82916 | 80000 | 80100 | 80000 | 403392 | 1874368 | 0 | 1452 | 49 | 37559 | 40782 | 40718 | 30741 | 3 | 30737 | 160100 | 200 | 80000 | 200 | 240000 | 40709 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80894 | 0 | 4198 | 430 | 3 | 867 | 80505 | 245 | 887 | 48 | 1565 | 81447 | 507 | 4330 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40919 | 80349 | 80000 | 80100 | 40742 | 40730 | 40746 | 40710 | 40875 |
| 80204 | 40779 | 305 | 0 | 0 | 1689 | 857 | 803 | 1 | 592 | 115 | 132 | 40786 | 762 | 1846 | 1597 | 158 | 66 | 160964 | 84099 | 80000 | 80100 | 80000 | 403152 | 1871560 | 0 | 282 | 49 | 37777 | 40842 | 40710 | 30757 | 3 | 30755 | 160100 | 200 | 80000 | 200 | 240000 | 40842 | 81 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80894 | 0 | 4488 | 461 | 4 | 895 | 80498 | 243 | 885 | 84 | 1720 | 81365 | 563 | 3954 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40836 | 80574 | 80000 | 80100 | 40782 | 40766 | 40830 | 40769 | 40733 |
| 80204 | 40780 | 307 | 0 | 0 | 1851 | 770 | 804 | 1 | 696 | 114 | 124 | 40769 | 761 | 1678 | 1812 | 146 | 25 | 161165 | 80485 | 80060 | 80100 | 80000 | 409863 | 1872832 | 0 | 358 | 49 | 37652 | 40796 | 40797 | 30740 | 3 | 30684 | 160100 | 200 | 80000 | 200 | 240000 | 40826 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80875 | 0 | 4207 | 443 | 4 | 851 | 80503 | 248 | 843 | 52 | 1659 | 81407 | 494 | 4478 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 40829 | 80381 | 80000 | 80100 | 40886 | 40738 | 40788 | 40782 | 40778 |
Result (median cycles for code divided by count): 0.5101
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80029 | 40742 | 306 | 0 | 0 | 0 | 1938 | 834 | 845 | 1 | 696 | 112 | 96 | 40816 | 787 | 1756 | 1641 | 133 | 25 | 160765 | 80631 | 80000 | 80010 | 80000 | 400785 | 1878712 | 231 | 49 | 37704 | 40764 | 40822 | 30795 | 3 | 30821 | 160010 | 20 | 80000 | 20 | 240000 | 40820 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80963 | 12 | 4274 | 452 | 6 | 861 | 80516 | 259 | 0 | 824 | 36 | 1661 | 81482 | 530 | 3927 | 14 | 2 | 5020 | 0 | 3 | 16 | 1 | 1 | 40777 | 80431 | 80000 | 80010 | 40766 | 40842 | 40723 | 40757 | 40835 |
| 80024 | 40899 | 306 | 1 | 0 | 1 | 1932 | 849 | 789 | 1 | 656 | 122 | 148 | 40741 | 823 | 1650 | 1728 | 189 | 25 | 165377 | 83505 | 80000 | 80010 | 80000 | 401749 | 1875544 | 738 | 49 | 37751 | 40748 | 40791 | 30724 | 3 | 30839 | 160010 | 20 | 80000 | 20 | 240000 | 40902 | 82 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80933 | 0 | 4518 | 509 | 8 | 894 | 80537 | 273 | 0 | 835 | 46 | 1721 | 81423 | 470 | 3804 | 0 | 0 | 5020 | 0 | 1 | 17 | 1 | 3 | 40770 | 80433 | 80000 | 80010 | 40756 | 40740 | 40798 | 40813 | 40861 |
| 80024 | 40818 | 307 | 0 | 0 | 0 | 1878 | 850 | 816 | 2 | 712 | 112 | 132 | 40725 | 784 | 1768 | 1644 | 158 | 25 | 160492 | 80674 | 80000 | 80010 | 80000 | 401214 | 1876840 | 1756 | 49 | 37812 | 40709 | 40834 | 30798 | 3 | 30906 | 160010 | 20 | 80000 | 20 | 240000 | 40861 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80881 | 0 | 4304 | 512 | 10 | 860 | 80561 | 284 | 0 | 894 | 78 | 1638 | 81378 | 525 | 3540 | 0 | 0 | 5020 | 0 | 1 | 16 | 1 | 1 | 40866 | 80454 | 80000 | 80010 | 40764 | 40856 | 40845 | 40823 | 40787 |
| 80024 | 40774 | 306 | 0 | 0 | 0 | 1920 | 886 | 821 | 1 | 696 | 123 | 84 | 40820 | 765 | 1518 | 1798 | 155 | 25 | 169639 | 80672 | 80000 | 80010 | 80000 | 401350 | 1875352 | 273 | 49 | 37835 | 40800 | 40794 | 30739 | 3 | 30748 | 160010 | 20 | 80000 | 20 | 240000 | 40754 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80925 | 0 | 4360 | 512 | 8 | 881 | 80553 | 277 | 0 | 905 | 32 | 1675 | 81488 | 557 | 3555 | 0 | 0 | 5020 | 0 | 1 | 16 | 1 | 1 | 40853 | 80498 | 80000 | 80010 | 40818 | 40828 | 40818 | 40759 | 40844 |
| 80024 | 40782 | 306 | 0 | 0 | 0 | 1866 | 870 | 791 | 1 | 696 | 110 | 96 | 40892 | 784 | 1627 | 1534 | 123 | 25 | 160448 | 86401 | 80000 | 80010 | 80000 | 400738 | 1874488 | 125 | 49 | 37721 | 40796 | 40792 | 30785 | 3 | 30840 | 160010 | 20 | 80000 | 20 | 240000 | 40743 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80873 | 0 | 4040 | 486 | 7 | 846 | 80479 | 268 | 0 | 881 | 38 | 1552 | 81450 | 536 | 3918 | 0 | 0 | 5020 | 0 | 1 | 18 | 1 | 1 | 40719 | 83863 | 80000 | 80010 | 40879 | 40765 | 40775 | 40802 | 40869 |
| 80024 | 40788 | 305 | 0 | 0 | 0 | 2064 | 841 | 788 | 1 | 672 | 101 | 100 | 40827 | 806 | 1859 | 1788 | 142 | 25 | 160380 | 80798 | 80100 | 80010 | 80000 | 402547 | 1873048 | 264 | 49 | 37687 | 40690 | 40828 | 30729 | 3 | 30835 | 160010 | 20 | 80000 | 20 | 240000 | 40823 | 82 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80877 | 0 | 3743 | 470 | 9 | 835 | 80574 | 265 | 0 | 895 | 68 | 1651 | 81507 | 530 | 3479 | 0 | 0 | 5020 | 0 | 1 | 16 | 1 | 1 | 40867 | 80289 | 80000 | 80010 | 40806 | 40778 | 40841 | 40756 | 40769 |
| 80024 | 40855 | 309 | 0 | 0 | 0 | 1758 | 827 | 827 | 1 | 704 | 115 | 92 | 40811 | 748 | 1931 | 1768 | 157 | 25 | 160407 | 80380 | 80032 | 80010 | 80000 | 402153 | 1872088 | 263 | 49 | 37652 | 40738 | 40707 | 30750 | 3 | 30741 | 160010 | 20 | 80120 | 20 | 240000 | 40914 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 81195 | 0 | 4057 | 522 | 72 | 899 | 80575 | 269 | 4 | 890 | 68 | 1660 | 81449 | 569 | 3900 | 0 | 0 | 5020 | 0 | 1 | 16 | 1 | 1 | 40832 | 80472 | 80000 | 80010 | 40736 | 40730 | 40772 | 40811 | 40831 |
| 80024 | 40752 | 304 | 0 | 0 | 1 | 1953 | 734 | 786 | 1 | 696 | 118 | 148 | 40789 | 779 | 1896 | 1638 | 147 | 25 | 160629 | 80245 | 80000 | 80010 | 80000 | 401951 | 1872478 | 2307 | 49 | 37724 | 40798 | 40801 | 30678 | 3 | 30761 | 160010 | 20 | 80000 | 20 | 240000 | 40809 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80919 | 0 | 4172 | 440 | 6 | 885 | 80540 | 261 | 0 | 856 | 36 | 1615 | 81488 | 506 | 4026 | 0 | 0 | 5020 | 0 | 2 | 16 | 1 | 1 | 40803 | 83289 | 80000 | 80010 | 40802 | 40815 | 40746 | 40770 | 40836 |
| 80024 | 40827 | 305 | 0 | 0 | 0 | 1797 | 848 | 784 | 1 | 712 | 137 | 136 | 40796 | 795 | 1577 | 1695 | 135 | 25 | 160634 | 87039 | 80005 | 80010 | 80000 | 402102 | 1874574 | 300 | 49 | 37708 | 40777 | 40805 | 30727 | 3 | 30891 | 160010 | 20 | 80000 | 20 | 240000 | 40892 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80886 | 0 | 3731 | 505 | 7 | 858 | 80493 | 278 | 0 | 846 | 36 | 1507 | 81355 | 529 | 3946 | 0 | 0 | 5020 | 0 | 1 | 17 | 1 | 1 | 40792 | 80149 | 80000 | 80010 | 40772 | 40807 | 40880 | 40833 | 40851 |
| 80024 | 40848 | 305 | 0 | 0 | 0 | 1884 | 872 | 778 | 1 | 728 | 135 | 120 | 40768 | 799 | 1651 | 1685 | 132 | 25 | 167959 | 86149 | 80000 | 80010 | 80000 | 416906 | 1877536 | 757 | 49 | 37669 | 40817 | 40810 | 30739 | 3 | 30700 | 160010 | 20 | 80000 | 20 | 240000 | 40806 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80871 | 0 | 3679 | 486 | 4 | 878 | 80503 | 270 | 0 | 937 | 126 | 1721 | 81402 | 520 | 3527 | 0 | 0 | 5020 | 0 | 3 | 17 | 1 | 1 | 40842 | 80594 | 80000 | 80010 | 40820 | 40771 | 40893 | 40750 | 40808 |