Firestorm: LDUR (64-bit) measurements

Code:

  ldur x0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	2	0	1	1	0	44	1	0	2	383	2	1	12	16	25	1000	1000	1000	15274	0	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	39	44	73	7	16	7	7	395	13	10	7	1000	399	399	399	399	399
1004	398	3	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	398	217	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1039	0	38	1038	6	1	39	44	73	6	16	7	7	395	14	14	7	1000	399	395	399	399	399
1004	398	3	0	0	0	0	44	0	0	1	379	2	1	1	19	25	1000	1000	1000	15274	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1039	0	38	1038	6	1	38	44	73	6	16	7	7	395	10	10	7	1000	399	399	399	399	399
1004	398	3	0	0	0	0	44	0	0	1	383	2	1	12	16	25	1000	1000	1000	15208	1	398	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	44	1040	0	38	1038	6	1	38	44	73	7	16	7	7	395	14	14	7	1000	399	399	395	399	399
1004	398	3	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	44	1039	0	38	1038	6	1	38	44	73	7	16	7	7	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	7	16	6	6	395	10	14	7	1000	399	399	395	395	399
1004	398	3	0	0	0	0	44	0	0	1	383	2	12	12	19	25	1000	1000	1000	15267	1	398	398	217	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	7	16	7	7	395	10	10	7	1000	399	395	395	399	399
1004	398	3	0	0	0	0	44	0	0	1	383	2	1	1	16	25	1000	1000	1000	15274	1	394	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1038	0	39	1038	6	1	38	44	73	6	16	7	6	395	14	14	7	1000	395	395	395	399	399
1004	398	3	0	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1038	0	38	1038	6	1	38	44	73	7	16	7	7	395	14	14	7	1000	399	395	395	399	399
1004	398	3	0	0	0	0	45	0	0	1	379	2	1	1	19	25	1000	1000	1000	15274	1	398	398	217	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	7	16	7	7	395	14	14	7	1000	399	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldur x0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	1	1	0	0	0	0	1	0	1	0	70036	69782	59749	25	40100	30100	10001	30111	10007	615549	3342423	0	49	66971	0	70035	70051	64700	6	65000	40118	30230	10010	60260	10010	70087	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	1	1	1	2619	1	16	1	1	69861	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	1	1	0	0	0	0	1	0	1	0	70036	69782	59749	25	40100	30103	10001	30111	10007	615549	3342423	0	49	66971	0	70051	70051	64700	6	65000	40118	30230	10010	60260	10010	70129	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	1	1	1	1	2619	1	16	1	1	69861	30000	0	0	0	10000	30100	70036	70052	70052	70052	70059
40204	70051	525	1	1	0	0	0	0	1	0	1	0	70036	69764	59710	25	40104	30100	10000	30100	10000	616014	3341470	0	49	66971	0	70051	70035	64631	3	64954	40100	30200	10000	60200	10000	70134	35	5	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	0	0	0	0	2610	2	71	2	2	69814	30003	10	10	10	10000	30100	70052	70052	70052	70036	70052
40204	70035	524	0	0	0	0	0	0	1	0	1	0	70036	69782	59695	25	40100	30103	10001	30100	10000	616014	3341470	0	49	66972	0	70051	70051	64647	3	64954	40100	30200	10000	60200	10000	70064	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69814	30003	10	0	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	13	0	1	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616175	3342254	0	49	66971	0	70109	70054	64648	3	64954	40100	30200	10000	60200	10000	70103	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69814	30003	10	10	0	10000	30100	70052	70036	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	1	0	1	0	70036	69782	59695	25	40100	30103	10000	30100	10000	616014	3341470	0	49	66971	0	70051	70051	64631	3	64954	40100	30200	10000	60200	10000	70135	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69798	30003	10	10	10	10000	30100	70052	70052	70036	70052	70052
40204	70114	525	0	0	0	0	0	0	0	0	0	0	70039	69782	59710	25	40104	30103	10000	30100	10000	616023	3341470	0	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	10000	70147	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	3	10000	1	0	0	0	0	2610	2	71	2	2	69819	30000	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	6	0	1	0	70036	69782	59695	25	40120	30103	10001	30100	10000	616175	3342254	0	49	66971	0	70035	70035	64647	3	64954	40100	30200	10000	60200	10000	70140	35	5	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	1	0	0	0	2610	2	71	2	2	69814	30003	0	10	10	10000	30100	70052	70052	70052	70036	70036
40204	70035	525	0	0	0	0	0	0	1	0	1	0	70036	69787	59695	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	0	70051	70051	64647	3	64938	40100	30200	10000	60200	10000	70164	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	0	0	0	2610	2	71	2	2	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70036
40204	70051	525	0	0	0	0	0	0	1	0	0	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	0	70035	70051	64647	3	64938	40100	30200	10000	60200	10000	70149	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	0	0	0	0	0	2610	2	71	2	2	69814	30003	10	10	10	10000	30100	70036	70052	70052	70036	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	1	1	1	0	0	0	1	1	0	1	70039	69777	59712	25	40014	30016	10002	30010	10000	617009	3342350	0	49	66973	0	70053	70053	64671	3	64978	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	1	10003	0	0	1	10000	1	1	1	1	0	0	2520	0	4	71	4	6	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70089
40024	70047	524	0	0	0	0	0	0	1	1	0	0	70073	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64670	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	4	71	4	4	69810	30003	6	6	6	10000	30010	70049	70048	70048	70048	70048
40024	70047	524	0	0	0	0	0	0	1	1	0	0	70080	69746	59709	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	4	71	6	4	69810	30003	6	6	6	10000	30010	70048	70052	70048	70048	70048
40024	70047	525	0	0	0	0	0	1	1	1	0	0	70033	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	4	71	4	4	69810	30003	6	6	0	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	0	0	0	1	1	0	0	70033	69730	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	4	71	4	4	69810	30003	6	0	6	10000	30010	70048	70048	70048	70048	70048
40024	70035	525	0	0	0	0	0	0	1	1	0	0	70061	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70035	70047	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	5	71	4	4	69810	30000	6	6	6	10000	30010	70048	70048	70048	70048	70402
40024	70048	525	0	0	0	0	0	1	568	1	0	0	70076	69730	59707	124	40014	30013	10001	30584	10000	616952	3342110	0	49	66968	0	70052	70050	64669	3	64975	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	4	71	4	4	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	0	0	0	1	1	0	0	70071	69732	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70049	70047	64665	3	64972	40010	30020	10000	60020	10000	70039	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	4	71	6	4	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	0	0	0	6	0	0	0	70040	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64711	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	0	4	71	4	5	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	0	0	0	1	1	0	0	70032	69743	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	0	70047	70047	64665	3	65033	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	150	10000	1	0	1	0	0	0	2520	0	5	71	4	4	69798	30003	6	6	6	10000	30010	70048	70048	70036	70048	70048

Test 3: throughput

Count: 8

Code:

  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26729	200	0	0	0	0	44	0	0	1	26716	2	1	12	22	25	80100	100	80000	100	80000	500	1166525	0	49	23651	26731	26731	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	43	80038	0	38	80000	6	1	39	43	5110	1	16	1	1	26728	0	14	10	7	80000	100	26735	26732	26728	26732	26807
80204	26709	200	0	0	0	0	44	0	0	1	26712	2	0	1	22	25	80100	100	80000	100	80000	500	1177038	0	49	23651	26731	26731	16654	3	16665	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	43	80000	0	38	80038	6	1	38	44	5110	1	16	1	1	26728	0	14	14	7	80000	100	26851	26738	26735	26738	26732
80204	26731	200	0	0	0	0	44	1	0	1	26716	2	1	12	22	25	80100	100	80000	100	80000	500	1165556	0	49	23653	26731	26731	16650	3	16685	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	43	80038	0	38	80038	6	1	39	44	5110	1	16	1	1	26728	0	0	7	4	80000	100	26817	26741	26733	26732	26728
80204	26741	200	0	0	0	0	44	0	0	1	26712	0	1	12	33	25	80100	100	80000	100	80000	500	1167127	0	49	23805	27028	26904	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	43	80038	0	38	80038	6	1	39	44	5110	1	16	1	1	26704	0	0	14	7	80000	100	26825	26737	26735	26803	26732
80204	26707	200	0	0	0	0	45	0	0	1	26716	2	1	1	22	25	80100	100	80000	100	80000	500	1167127	0	49	23651	26731	26731	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	44	80039	0	39	80038	6	1	0	44	5110	1	16	1	1	26728	0	14	10	4	80000	100	26728	26732	26882	26784	26732
80204	26727	200	0	0	0	0	45	1	0	0	26692	2	1	12	95	25	80100	100	80000	100	80000	500	1165556	1	49	23651	26727	26731	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	44	80038	0	39	80039	6	1	39	44	5110	2	16	1	1	26728	0	14	10	7	80000	100	26732	26732	26732	26732	26714
80204	26731	200	0	0	0	0	45	0	0	1	26716	2	12	12	22	25	80100	100	80000	100	80000	500	1167127	0	49	23651	26727	26727	16650	3	16685	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	43	80039	0	39	80038	0	1	39	44	5110	1	16	1	1	26704	0	14	10	7	80000	100	26841	26729	26731	26739	26732
80204	26731	200	0	0	0	0	44	0	0	0	26716	2	1	1	22	25	80100	100	80000	100	80000	500	1168312	1	49	23651	26731	26731	16654	3	16685	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80039	0	38	80000	6	0	39	43	5110	1	16	1	1	26728	0	0	10	7	80000	100	26822	26736	26737	26734	26736
80204	26731	200	0	0	0	0	44	0	0	1	26716	3	0	12	91	25	80100	100	80000	100	80000	500	1165556	0	49	23647	26731	26727	16654	3	16665	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	43	80039	0	39	80038	6	1	38	44	5110	1	16	1	1	26728	0	10	14	7	80000	100	26838	26737	26737	26741	26728
80204	26731	201	1	1	0	0	44	0	0	1	26716	2	1	1	23	25	80100	100	80000	100	80000	500	1165556	0	49	23627	26727	26731	16654	3	16685	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	100	80000	43	80039	0	38	80038	6	0	38	0	5110	1	16	1	1	26728	0	10	0	7	80000	100	26820	26737	26732	26770	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	1	0	0	0	57	1	1	26712	2	12	1	19	25	80010	10	80000	10	80000	50	1167501	1	0	49	23647	26739	26734	16672	3	16688	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80000	0	38	80038	6	1	39	44	5020	17	16	17	17	26724	0	14	10	7	80000	10	26732	26732	26732	26732	26732
80024	26731	207	0	0	0	0	62	1	0	26716	0	1	1	19	25	80010	10	80000	10	80000	50	1168843	0	0	49	23651	26829	26745	16681	3	16688	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80038	0	54	80038	0	0	39	44	5020	15	16	14	17	26728	0	10	10	0	80000	10	26732	26732	26709	26732	26732
80024	26708	200	0	0	0	0	6	0	0	26693	2	1	0	19	25	80010	10	80000	10	80000	50	1167124	0	0	49	23651	26802	26735	16681	3	16711	80010	20	80000	20	80000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80038	0	0	80000	6	0	39	44	5020	17	16	16	16	26725	0	14	10	0	80000	10	26709	26732	26732	26732	26794
80024	26731	200	0	0	0	0	86	0	1	26716	2	0	0	0	25	80010	10	80000	10	80000	50	1167124	0	1	49	23653	26832	26740	16682	3	16688	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80000	0	38	80000	6	0	38	44	5020	17	16	16	12	26728	0	0	0	7	80000	10	26709	26709	26709	26732	26732
80024	26731	200	0	0	0	0	92	1	0	26716	2	1	1	0	25	80010	10	80000	10	80000	50	1166750	0	0	49	23651	26727	26731	16672	10	16840	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	44	80038	0	38	80038	6	1	38	44	5020	17	16	17	17	26728	0	0	14	7	80000	10	26728	26732	26732	26732	26732
80024	26731	200	0	0	0	0	44	0	0	26693	2	0	1	0	25	80010	10	80000	10	80000	50	1166750	0	0	49	23651	26708	26731	16652	3	16722	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80038	0	38	80039	6	1	0	43	5020	17	16	17	18	26724	0	14	0	7	80000	10	26732	26732	26733	26732	26736
80024	26708	200	0	0	0	0	30	1	1	26716	2	12	1	20	25	80010	10	80000	10	80000	50	1167124	0	0	49	23628	26728	26731	16676	3	16719	80010	20	80000	20	80000	26731	80	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80168	0	38	80038	6	0	38	44	5020	15	16	10	17	26728	0	14	0	0	80000	10	26709	26732	26732	26732	26728
80024	26731	200	0	0	0	0	44	1	0	26693	0	0	12	0	25	80010	10	80000	10	80000	50	1167124	0	0	49	23651	26708	26708	16676	3	16696	80010	20	80000	20	80000	26708	80	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80000	0	38	80038	6	0	39	44	5020	14	16	17	9	26730	0	0	0	7	80000	10	26732	26709	26728	26709	26732
80024	26731	200	0	0	0	0	59	0	1	26716	2	1	0	19	25	80010	10	80000	10	80000	50	1167201	0	0	49	23628	26840	26712	16682	3	16711	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	0	80038	0	38	80000	6	1	0	44	5020	16	16	17	17	26705	0	0	14	0	80000	10	26732	26732	26732	26732	26732
80024	26731	200	1	0	0	0	56	1	1	26713	0	1	12	16	25	80010	10	80000	10	80000	50	1167124	0	0	49	23628	26731	26728	16652	3	16688	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80038	0	38	80038	6	0	39	44	5020	16	16	18	10	26725	0	14	14	0	80000	10	26732	26732	26728	26709	26732

LDUR (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations