Firestorm: EON (register, asr, 64-bit) measurements

Code:

  eon x0, x0, x1, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	16	12	61	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	1	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2326	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1754	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	17	9	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	103	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	156	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	6	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  eon x0, x0, x1, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	160	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10541	21202	20081	42	2	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	161	0	18	306	10000	19803	25	20100	20100	10100	187172	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	2015	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	160	0	0	66	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	2	0	710	0	1	71	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	0	0	82	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	161	0	0	343	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	161	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20082	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	160	1	0	537	10000	19743	25	20010	20010	10010	185310	0	49	17091	0	20035	20035	18451	3	18718	10010	10020	20358	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	4	89	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	313	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	117	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	9	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	3	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	0	726	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	145	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	15	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	0	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  eon x0, x1, x0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	155	24	0	103	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	21	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	3	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	7	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	2	0	1	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	12	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	15	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	24	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	6	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	9	0	103	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	12	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20076	160	1	0	0	0	0	0	0	453	10000	19743	25	20010	20012	10012	185298	0	49	16955	20035	20035	18451	3	18722	10012	10020	20020	20035	44	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	0	2	59	3	2	19792	20002	10010	20036	20036	20036	20036	20036
10024	20035	155	1	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	2	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18453	3	18722	10012	10020	20020	20035	44	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	161	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	1	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	0	0	0	0	0	0	0	61	10000	19741	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	4	0	0	0	0	2045	640	5	2	59	3	4	19793	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185298	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	0	2	59	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	0	1	0	0	0	0	61	10000	19743	25	20010	20010	10010	185298	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20079	155	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185298	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	642	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  eon x0, x8, x9, asr #17
  eon x1, x8, x9, asr #17
  eon x2, x8, x9, asr #17
  eon x3, x8, x9, asr #17
  eon x4, x8, x9, asr #17
  eon x5, x8, x9, asr #17
  eon x6, x8, x9, asr #17
  eon x7, x8, x9, asr #17

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80204	26769	214	0	0	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	156	0	5110	2	22	1	1	26717	160267	0	80100	26726	26726	26726	26726	26726
80204	26725	214	0	0	0	6	173	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	0	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	0	0	0	0	726	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	0	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	0	0	0	12	103	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	165	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	0	0	0	0	378	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	12	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	214	0	0	0	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	3	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	214	0	0	0	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	174	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	0	0	0	0	738	80000	26094	25	160100	160100	80110	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	174	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	0	0	0	0	61	80000	26094	25	160100	160100	80100	168255	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	150	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726
80204	26725	207	0	0	0	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	0	80100	100	0	153	0	5110	1	22	1	1	26717	160000	0	80100	26726	26726	26726	26726	26726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26735	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160179	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	199	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26825	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26799	26800	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	1	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26771
80024	26769	207	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712

EON (register, asr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations