Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

EON (register, asr, 64-bit)

Test 1: uops

Code:

  eon x0, x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203516126110001735252000200010003257012035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351506110001735252000200010003257012035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351606110001735252000200010003257002035203515753184210001000200020354211100110001000731671117812000100020362036203620362036
100420351606110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351606110001735252000200010003257002035203515753184210001000232620354211100110000000731671117812000100020362036203620362036
100420351506110001754252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351796110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351606110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
1004203516010310001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
1004203516015610001735252000200010003257012035203515756184210001000200020354211100110000000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  eon x0, x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003516000611000019803252010020100101001853420491695502003520035184293187001010010541212022008142211020110099100101001000000007100159111979120000101002003620036200362003620036
10204200351610183061000019803252010020100101001871720491695502003520035184293187001010010200202002003542111020110099100101001000000007100159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853420491695502003520035184293187001010010200202002003542111020110099100101001000002015007100159111979120000101002003620036200362003620036
102042003516000661000019803252010020100101001853420491695502003520035184293187001010010200202002003542111020110099100101001000000007100159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853420491695502003520035184293187001010010200202002003542111020110099100101001000000207100171111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853420491695502003520035184293187001010010200202002003542111020110099100101001000000007100159111979120000101002003620036200362003620036
102042003515600821000019803252010020100101001853420491695502003520035184293187001010010200202002003542111020110099100101001000000007100159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853420491695502003520035184293187001010010200202002003542111020110099100101001000000007100159111979120000101002003620036200362003620036
1020420035161003431000019803252010020100101001853420491695502003520035184293187001010010200202002003542111020110099100101001000000007100159111979120000101002003620036200362003620036
102042003516100611000019803252010020100101001853420491695502008220035184293187001010010200202002003542111020110099100101001000000007100159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035160105371000019743252001020010100101853100491709102003520035184513187181001010020203582003542111002110910100101000640489221979220000100102003620036200362003620036
1002420035161003131000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
1002420035161001171000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101009640263221979220000100102003620036200362003620036
100242003516100611000019743252001020010100101853100491695532003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515500611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515500611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
1002420035155007261000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
1002420035161001451000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
1002420035161006110000197432520010200101001018531004916955020035200351845115187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003516100611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  eon x0, x1, x0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035155240103100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
102042003515621061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351553061100001980325201002010010100185342149169552003520035184297187001010010200202002003542111020110099100101001002010710159111979120000101002003620036200362003620036
102042003515512061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
102042003515515061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710259111979120000101002003620036200362003620036
102042003515524061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351556061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351550061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
102042003515590103100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
102042003515512061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)0918191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200761601000000453100001974325200102001210012185298049169552003520035184513187221001210020200202003544111002110910100101000000006400259321979220002100102003620036200362003620036
1002420035155100000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000000006400263221979220000100102003620036200362003620036
1002420035155000000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000002006400263221979220000100102003620036200362003620036
1002420035161000000061100001974325200102001010010185310049169552003520035184533187221001210020200202003544111002110910100101000000006400263221979220000100102003620036200362003620036
1002420035161000000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000000006400263221979220000100102003620036200362003620036
1002420035155100000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000000006400263221979220000100102003620036200362003620036
1002420035156000000061100001974125200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101004000020456405259341979320000100102003620036200362003620036
1002420035155000000061100001974325200102001010010185298049169552003520035184513187181001010020200202003542111002110910100101000000006400259221979220000100102003620036200362003620036
1002420035155001000061100001974325200102001010010185298049169552003520035184513187181001010020200202003542111002110910100101000000006400263221979220000100102003620036200362003620036
1002420079155000000061100001974325200102001010010185298049169552003520035184513187181001010020200202003542111002110910100101000000006420263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  eon x0, x8, x9, asr #17
  eon x1, x8, x9, asr #17
  eon x2, x8, x9, asr #17
  eon x3, x8, x9, asr #17
  eon x4, x8, x9, asr #17
  eon x5, x8, x9, asr #17
  eon x6, x8, x9, asr #17
  eon x7, x8, x9, asr #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? int retires (ef)f5f6f7f8fd
802042676921400006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910008010010001560511022211267171602670801002672626726267262672626726
80204267252140006173800002609425160100160100801001643180492364526725267251661531667780100802001602002672539118020110099100080100100000511012211267171600000801002672626726267262672626726
80204267252070000726800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100080100100000511012211267171600000801002672626726267262672626726
80204267252070001210380000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910008010010001650511012211267171600000801002672626726267262672626726
802042672520700003788000026094251601001601008010016431814923645267252672516615316677801008020016020026725391180201100991000801001000120511012211267171600000801002672626726267262672626726
8020426725214000061800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100080100100030511012211267171600000801002672626726267262672626726
802042672521400006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910008010010001740511012211267171600000801002672626726267262672626726
8020426725207000073880000260942516010016010080110164318149236452672526725166153166778010080200160200267253911802011009910008010010001740511012211267171600000801002672626726267262672626726
802042672520700006180000260942516010016010080100168255149236452672526725166153166778010080200160200267253911802011009910008010010001500511012211267171600000801002672626726267262672626726
802042672520700006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910008010010001530511012211267171600000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242673520000618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160179800102671226712267122671226712
800242671120700618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102671226712267122671226712
800242671120000618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102671226712267122671226712
800242671119900618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102671226712267122671226712
800242671120000618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102682526712267122671226712
800242671120000618000021280251600101600108001016314204923631267992680016623316685800108002016002026711391180021109108001010000150201221126704160000800102671226712267122671226771
800242676920700618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102671226712267122671226712
800242671120000618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102671226712267122671226712
800242671120000618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102671226712267122671226712
800242671120000618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000050201221126704160000800102671226712267122671226712