Firestorm: LDR (post-index, 32-bit) measurements

Code:

  ldr w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	7	0	0	0	0	1	56	0	0	0	2	0	1025	11	1	1	11	14	25	2000	1000	1000	1000	1000	52840	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1010	0	1	58	1027	1	1	14	0	19	1028	36	5	8	32	0	0	73	1	16	1	1	1037	1000	24	26	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	1	0	0	58	0	0	0	1	0	1025	0	1	1	1	23	25	2000	1000	1000	1000	1000	52840	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1016	0	1	52	1027	1	2	16	6	23	1028	53	8	18	56	0	0	73	1	16	1	1	1037	1000	28	26	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	1	1	70	10	1	0	1	0	1025	4	0	1	1	11	25	2000	1000	1000	1000	1000	52844	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1008	0	0	41	1027	1	1	10	0	19	1022	35	5	8	32	0	0	73	1	16	1	1	1037	1000	24	25	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	1	0	0	143	7	1	0	1	0	1025	6	1	2	2	14	25	2000	1000	1000	1000	1000	52840	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1015	0	1	50	1021	1	0	8	0	10	1020	42	4	8	32	0	23	73	1	16	1	1	1037	1000	24	27	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	0	0	32	8	1	0	0	0	1025	12	0	1	0	8	25	2000	1000	1000	1000	1000	52856	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1014	0	0	24	1007	1	1	22	8	17	1016	24	7	10	24	0	0	73	1	16	1	1	1037	1000	28	28	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	0	58	11	1	0	1	0	1025	3	1	3	3	8	25	2000	1000	1000	1000	1000	52836	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1012	0	2	69	1037	1	1	31	6	15	1034	44	7	16	72	0	0	73	1	16	1	1	1037	1000	34	37	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	0	50	14	0	0	1	0	1025	0	1	1	1	17	25	2000	1000	1000	1000	1000	52844	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1000	0	0	32	1008	0	1	0	0	13	1008	18	5	10	32	0	0	73	1	16	1	1	1037	1000	24	23	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	0	0	75	16	0	0	0	0	1025	10	1	3	1	9	25	2000	1000	1000	1000	1000	52848	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1000	0	1	41	1021	2	1	10	12	23	1022	41	6	12	56	0	0	73	1	16	1	1	1037	1000	36	43	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	1	0	0	62	8	1	0	1	28	1025	12	1	3	3	17	25	2000	1000	1000	1000	1000	52840	45824	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1000	0	0	41	1013	1	1	10	0	19	1022	41	4	12	56	0	0	73	1	16	1	1	1037	1000	24	26	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	1	1	0	1	40	14	0	0	0	0	1025	8	0	0	0	14	25	2000	1000	1000	1000	1000	52848	45827	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1000	0	0	56	1014	0	0	0	0	23	1015	36	6	11	56	0	0	73	1	16	1	1	1037	1000	24	23	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1753

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72081	539	1	1	1	3	0	0	0	0	0	598	0	845	1	0	744	1	156	71667	811	4	3	71442	25	50810	40612	10140	40100	10000	614534	2712818	0	0	49	68845	71828	71807	65408	3	65469	50100	40200	10000	70200	10000	71733	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10908	2	145	494	10676	259	9	912	110	29	10913	125	6	128	2	8	2	2610	0	2	51	1	1	71614	40611	992	870	936	10000	40100	71689	71709	71751	71881	71907
50204	71743	538	0	1	0	0	0	0	0	0	0	586	0	808	1	0	712	1	116	71802	814	4	3	71607	25	50770	40648	10125	40100	10000	674052	2718196	0	0	49	68759	71888	71736	65221	3	65542	50100	40200	10000	70200	10000	71756	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10915	2	164	516	10654	249	8	899	90	34	10917	120	5	133	2	2	1	2610	0	1	51	1	1	71841	40564	886	1044	886	10000	40100	71672	71812	71798	71871	71750
50204	71479	538	0	2	0	0	0	0	0	0	0	569	0	831	1	0	720	3	164	71691	809	3	4	71330	25	50725	40556	10130	40100	10000	674643	2722019	0	0	49	68701	71765	71759	65245	3	65402	50100	40200	10000	70200	10000	71700	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10923	6	121	534	10661	255	9	934	82	33	10929	133	7	120	2	2	8	2610	0	1	51	1	1	71425	40504	884	986	826	10000	40100	71798	71695	71793	71922	71799
50204	71761	537	0	1	1	0	0	0	0	0	0	579	0	827	1	0	720	2	92	71925	804	4	3	71398	25	50725	40604	10130	40100	10000	674724	2717072	0	0	49	68539	71683	71695	65404	3	65572	50100	40200	10000	70200	10000	71859	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10892	1	145	514	10678	264	8	930	46	42	10962	118	6	129	2	2	8	2610	0	1	51	1	1	71701	40532	912	912	902	10000	40100	71833	71987	71761	71748	71625
50204	71737	537	0	1	0	0	0	0	0	0	0	532	0	839	1	0	744	3	104	71598	787	3	3	71637	25	50760	40588	10133	40100	10000	676849	2718739	0	0	49	68718	71656	71831	65080	3	65375	50100	40200	10000	70200	10000	71702	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10914	2	128	486	10651	262	7	929	108	42	10949	137	4	121	3	4	4	2610	0	1	51	1	1	71690	40556	888	954	900	10000	40100	71793	71711	71994	71790	71713
50204	71657	537	0	1	0	0	0	0	0	0	0	550	0	827	1	0	712	2	100	72020	805	3	3	71628	25	50735	40668	10134	40100	10000	676659	2716404	0	0	49	68771	71672	71645	65089	3	65374	50100	40200	10000	70200	10000	71763	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10917	1	130	517	10649	245	8	914	24	31	10928	116	6	135	1	6	4	2610	0	1	51	1	1	71545	40588	934	900	838	10000	40100	71780	71826	71824	71807	71829
50204	71777	537	0	1	0	0	0	1	0	0	0	518	0	818	1	0	704	2	120	71590	813	4	3	71427	25	50790	40616	10131	40100	10000	676049	2714728	0	0	49	68695	71771	71883	65193	3	65388	50100	40200	10000	70200	10000	71673	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10917	2	147	526	10681	278	10	930	182	27	10939	129	6	131	2	0	4	2610	0	1	51	1	1	71582	40492	952	908	874	10000	40100	71812	71671	71769	71872	71574
50204	71815	537	0	1	0	0	0	0	0	0	0	559	0	821	1	0	680	1	76	71877	791	5	2	71608	25	50730	40596	10139	40100	10000	672504	2716365	0	0	49	68685	71656	71746	65259	3	65424	50100	40200	10000	70200	10000	71684	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10952	2	147	507	10673	282	18	981	124	35	10947	121	3	120	1	0	1	2610	0	1	51	1	1	71763	40532	942	834	858	10000	40100	71764	71940	71768	71815	71788
50204	71723	537	0	1	1	0	0	0	0	0	0	569	0	826	1	0	728	1	108	71721	795	2	3	71555	25	50805	40616	10137	40100	10000	676347	2717954	0	0	49	69035	71817	71757	65185	3	65461	50100	40200	10000	70200	10000	71676	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10930	1	155	517	10647	270	18	952	104	42	10947	133	6	132	3	1	7	2610	0	1	51	1	1	71607	40552	850	844	842	10000	40100	71804	71696	71798	71755	71580
50204	71733	537	0	2	0	0	0	0	0	0	0	534	0	833	1	0	728	1	108	71656	799	4	3	71524	25	50815	40636	10132	40100	10000	677337	2723086	0	0	49	68538	71979	71733	65219	3	65444	50100	40200	10000	70200	10000	71847	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10920	1	135	501	10638	274	7	895	88	29	10908	123	5	121	3	2	3	2610	0	1	51	1	2	71805	40556	884	932	890	10000	40100	71834	71601	71829	71766	71873

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1933

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72305	538	0	0	0	0	447	0	785	1	696	5	112	71867	796	4	1	71694	25	50710	40550	10139	40010	10000	612280	2726971	0	49	68730	72038	71805	65265	3	65512	50010	40020	10000	70020	10000	72051	35	1	1	40021	10	9	10	10000	30010	10000	10	10885	1	123	568	10642	256	12	926	162	22	10945	148	5	133	1	0	3	0	0	2520	7	85	2	5	71724	40524	1054	1028	997	10000	40010	71858	71774	71951	71884	71939
50024	71930	538	1	0	0	0	465	0	821	1	704	1	104	72013	792	3	0	71641	25	50690	40526	10137	40010	10000	613090	2728458	0	49	68771	71980	71900	65353	3	65615	50010	40020	10000	70020	10000	72118	35	1	1	40021	10	9	10	10000	30010	10000	10	10881	1	140	485	10658	264	13	919	78	26	10904	127	5	122	1	0	3	0	0	2520	4	85	5	5	71807	40544	1097	1115	1106	10000	40010	71979	71831	72047	72101	72048
50024	71890	540	1	1	0	0	419	0	829	1	784	2	208	71827	804	4	2	71661	25	50695	40570	10132	40010	10000	613178	2728890	1	49	66122	71918	71912	65323	3	65584	50010	40020	10000	70020	10000	72152	35	1	1	40021	10	9	10	10000	30010	10000	10	10915	1	154	508	10626	254	9	912	70	21	10954	138	4	130	1	0	5	0	0	2520	4	85	4	2	71727	40532	1011	1111	928	10000	40010	71905	72022	71997	71860	72045
50024	71894	538	1	0	0	0	440	0	834	1	728	3	268	71819	814	4	2	71677	25	50670	40550	10125	40010	10000	612928	2728523	0	49	68989	71825	71866	65425	3	65493	50010	40020	10000	70020	10000	71999	35	1	1	40021	10	9	10	10000	30010	10000	10	10891	2	160	505	10693	265	13	933	74	26	10930	128	6	114	1	0	3	0	0	2520	5	85	3	4	71617	40516	897	1090	990	10000	40010	72024	72014	71846	72028	71858
50024	71813	540	1	0	0	0	396	0	840	1	720	5	128	71933	829	5	1	71685	25	50720	40534	10127	40010	10000	613810	2728971	0	49	68975	71949	71853	65217	3	65440	50010	40020	10000	70020	10000	71971	35	1	1	40021	10	9	10	10000	30010	10000	10	10884	1	125	500	10671	264	7	906	80	18	10944	133	5	124	1	0	3	0	0	2520	4	85	4	4	71729	40544	1119	1097	1127	10000	40010	72042	72009	71963	72002	71973
50024	71826	540	1	0	0	0	452	0	829	1	720	2	88	71959	799	4	1	71636	25	50665	40530	10126	40010	10000	612316	2733920	0	49	68788	71928	71926	65336	3	65637	50010	40020	10000	70020	10000	71877	35	1	1	40021	10	9	10	10000	30010	10000	10	10932	2	135	509	10634	269	12	904	68	19	10924	128	6	126	1	0	3	0	0	2520	3	85	5	4	71658	40568	1061	1069	1139	10000	40010	71863	71947	71973	72043	72109
50024	72075	539	0	0	0	0	446	0	812	1	728	0	108	71675	767	4	0	71566	25	50675	40534	10131	40010	10000	611909	2727396	0	49	69003	71814	71990	65238	3	65580	50010	40020	10000	70020	10000	72064	35	1	1	40021	10	9	10	10000	30010	10000	10	10917	1	150	507	10670	263	8	906	92	23	10933	128	6	121	1	0	3	0	0	2520	4	85	4	3	71612	40544	1033	1083	1197	10000	40010	72252	72137	71691	72099	72047
50024	71891	539	1	1	0	0	443	0	831	1	768	4	108	71979	803	4	1	71847	25	50715	40530	10136	40010	10000	613972	2726163	0	49	68928	71952	71950	65487	3	65584	50010	40020	10000	70020	10000	72092	35	1	1	40021	10	9	10	10000	30010	10000	10	10992	2	144	486	10659	260	8	956	80	24	10940	146	5	133	1	0	3	0	0	2520	4	85	2	5	71694	40492	1221	1144	1156	10000	40010	72039	72012	72001	72016	71875
50024	71951	540	1	0	0	0	395	0	800	1	752	1	136	71949	792	4	0	71836	25	50620	40526	10126	40010	10000	612449	2724064	0	49	68896	71840	71861	65566	3	65444	50010	40020	10000	70020	10000	71871	35	1	1	40021	10	9	10	10000	30010	10000	10	10881	1	146	494	10656	257	9	906	122	5	10944	122	4	121	1	0	5	0	0	2520	2	85	4	4	71664	40536	1073	1043	1052	10000	40010	72013	71977	72067	71814	72055
50024	71794	539	1	0	1	0	451	0	822	1	744	3	108	72132	788	3	2	71678	25	50625	40542	10130	40010	10000	612823	2731574	0	49	68770	71954	71803	65133	3	65587	50010	40020	10000	70020	10000	72019	35	1	1	40021	10	9	10	10000	30010	10000	10	10897	1	135	496	10643	247	8	898	76	20	10928	133	4	118	1	0	3	0	0	2520	5	85	4	4	71871	40508	1077	1107	1052	10000	40010	71820	71939	72062	71994	72155

Test 3: throughput

Count: 8

Code:

  ldr w0, [x6], #8
  ldr w0, [x7], #8
  ldr w0, [x8], #8
  ldr w0, [x9], #8
  ldr w0, [x10], #8
  ldr w0, [x11], #8
  ldr w0, [x12], #8
  ldr w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	18	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	30044	222	1	2	0	0	7002	818	1	648	131	144	29271	793	333	1799	1725	2029	25	160177	80168	80000	80100	80000	400741	1290468	1	71	49	26275	29427	29489	9412	0	3	9404	160100	80200	80000	80200	80000	29206	35	1	1	80201	100	99	35	100	80000	100	80000	0	100	80940	20	423	5048	84712	678	17	884	122	4736	86646	782	128	5404	4590	0	9	5110	1	16	1	1	29767	29	80056	608	617	124	80000	80100	29369	29422	29210	29545	29288
160204	29494	222	0	0	0	0	6599	818	1	704	116	96	29230	797	366	1925	2085	2147	25	160158	80173	80000	80100	80000	400775	1299026	1	63	49	26211	29272	29483	9152	0	3	9410	160100	80200	80000	80200	80000	29154	35	1	1	80201	100	99	36	100	80000	100	80000	0	100	80932	0	393	6145	85780	701	13	932	66	5295	85918	780	124	5149	5474	0	3	5110	1	16	1	1	29504	42	80078	473	527	118	80000	80100	29384	29350	29574	29374	29255
160204	29515	219	0	0	0	0	7189	811	1	728	98	88	29459	821	354	1806	1723	2163	25	160156	80166	80000	80100	80165	401628	1299701	1	59	49	26421	29330	29311	9239	0	3	9296	160471	80200	80000	80200	80000	29363	35	1	1	80201	100	99	27	100	80000	100	80000	0	100	80912	0	373	5803	85453	738	15	919	54	5483	85761	768	143	5216	5505	3	0	5110	1	17	1	1	29510	33	80072	526	549	116	80000	80100	29669	29410	29329	29541	29603
160204	29513	221	0	0	0	0	7023	819	1	696	105	100	29258	812	393	1774	1895	2048	58	160478	80336	80130	80229	80161	401678	1293578	1	67	49	26323	29691	29132	9242	56	19	9373	160100	80372	80173	80200	80165	29304	35	1	1	80201	100	99	32	100	80000	100	80000	0	100	80866	0	420	5556	85260	625	10	890	50	4768	85675	780	133	4582	4827	3	7	5131	1	25	1	1	29456	22	80052	547	499	90	80000	80100	29506	29381	29427	29327	29437
160204	29461	220	0	0	0	0	6436	811	1	504	138	104	29184	821	397	1719	1826	1879	25	160163	80169	80000	80100	80000	400826	1301813	1	60	49	26129	29483	29345	9311	0	3	9377	160786	80200	80342	80200	80000	29539	35	1	1	80201	100	99	36	100	80000	100	80000	0	100	80888	0	393	5873	85924	688	13	895	40	5013	85854	799	129	4924	5041	0	7	5110	1	16	1	1	29430	24	80056	548	518	106	80000	80100	29432	29265	29453	29488	29454
160204	29536	222	0	0	0	0	6999	799	1	760	109	92	29446	805	361	1757	1819	2249	25	160165	80151	80000	80100	80000	400804	1302102	1	71	49	26272	29612	29317	9215	0	3	9437	160100	80200	80000	80200	80000	29376	35	1	1	80201	100	99	30	100	80000	100	80000	0	100	80913	0	390	5180	85628	628	14	931	36	5465	85467	760	121	4498	4186	3	4	5110	1	16	1	1	29114	22	80079	559	559	132	80000	80100	29254	29301	29116	29113	29530
160204	29449	218	0	0	0	0	7047	817	1	792	130	136	29144	783	361	1681	1704	2147	25	160156	80170	80000	80100	80000	400802	1304252	1	48	49	26311	29293	29484	9356	0	3	9630	160100	80200	80000	80200	80000	29545	35	1	1	80201	100	99	23	100	80000	100	80000	1	100	80889	0	370	5186	85347	683	11	919	48	5130	86281	836	135	5153	4754	0	4	5110	1	16	1	1	29541	38	80072	600	480	96	80000	80100	29573	29351	29360	29353	29347
160204	29472	221	0	0	0	0	6790	793	1	536	120	84	29414	810	357	1827	1956	1961	25	160177	80149	80000	80100	80000	400816	1298570	1	66	49	26291	29452	29429	9287	0	3	9382	160100	80200	80000	80200	80000	29489	35	1	1	80201	100	99	32	100	80000	100	80000	0	100	80930	0	414	5493	85544	659	10	875	32	5125	86508	837	117	4570	5042	0	3	5110	1	16	1	1	29574	29	80057	433	527	110	80000	80100	29417	29264	29112	29473	29225
160204	29270	219	0	0	0	0	7018	813	1	704	111	192	29478	799	364	1831	1862	2298	25	160146	80158	80000	80100	80000	400839	1304925	1	57	49	26377	29162	29294	8996	0	3	9241	160100	80200	80000	80200	80000	29308	35	1	1	80201	100	99	16	100	80000	100	80000	0	100	80883	0	387	6031	85866	651	11	924	38	5468	86221	814	153	5246	4964	0	9	5110	1	16	1	1	29344	26	80059	508	492	97	80000	80100	29818	29408	29535	29401	29322
160204	29585	223	0	0	2	4	7528	791	1	712	105	100	29261	807	344	2038	1949	2068	25	160160	80158	80000	80100	80177	400776	1310271	1	70	49	26398	29349	29329	9324	0	3	9315	160100	80200	80000	80200	80000	29330	35	1	1	80201	100	99	28	100	80000	100	80000	0	100	80878	0	422	5797	85187	686	13	909	38	5446	86553	800	129	4947	4691	0	3	5110	1	16	1	1	29335	27	80062	612	525	95	80000	80100	29668	29657	29757	29261	29470

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	1e	1f	20	22	23	24	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29875	222	1	1	0	0	0	7434	0	784	1	0	0	760	99	196	29541	788	621	1769	1837	2179	25	160082	80061	80000	80010	80000	400384	1305451	0	0	60	49	26590	29268	29485	9427	0	3	9412	160010	80020	80000	80020	80000	29510	35	1	1	80021	10	9	26	10	80000	10	80000	10	80923	38	332	5809	0	85789	615	13	903	52	5573	86357	937	143	5355	5356	52	0	0	0	5020	1	16	0	1	1	29577	25	80064	591	552	123	80000	80010	29425	29457	29346	29424	29466
160024	29690	220	3	3	0	0	0	7416	264	803	1	0	0	696	132	188	29641	819	599	1718	2053	2116	25	160080	80085	80000	80010	80000	400356	1297787	0	0	77	49	26341	29620	29731	9562	0	18	9640	160010	80020	80165	80020	80000	29689	35	3	1	80021	10	9	22	10	80000	10	80000	10	80987	59	428	6403	30	85638	624	12	879	32	6084	86317	794	133	4894	5588	56	0	0	0	5020	1	16	0	1	1	29823	37	80082	584	542	100	80000	80010	29420	29534	29463	29621	29647
160024	29443	219	3	0	1	0	0	7658	0	810	1	0	0	720	102	300	29550	819	768	2039	1734	2215	25	160087	80079	80130	80010	80173	401159	1303128	0	0	69	49	26427	29599	29478	9563	0	3	9532	160010	80020	80000	80020	80000	29590	35	1	1	80021	10	9	26	10	80000	10	80000	10	80927	56	354	5279	0	85540	618	11	924	74	5794	86931	768	121	5460	4974	73	0	5	0	5020	1	16	0	1	1	29866	37	80079	530	536	112	80000	80010	29545	29564	29602	29450	29440
160024	29783	220	3	3	0	0	0	7298	0	855	1	0	0	648	98	164	29517	790	599	1886	2075	2078	25	160074	80067	80000	80010	80000	400321	1307414	0	0	71	49	26522	29694	29631	9604	0	3	9518	160010	80020	80000	80020	80000	29417	35	1	1	80021	10	9	29	10	80000	10	80000	10	80941	49	331	5676	0	86069	647	16	869	50	5488	86535	723	137	5560	4890	51	2	9	0	5020	1	16	0	1	1	29916	26	80057	600	501	103	80000	80010	29474	29603	29328	29453	29384
160024	29656	222	3	0	1	0	0	7653	0	820	1	0	0	592	93	324	29563	764	680	2096	2068	2239	25	160073	80412	80000	80010	80000	400372	1293252	0	0	54	49	26372	29732	29341	9516	43	3	9614	160010	80020	80000	80020	80000	29421	35	1	1	80021	10	9	16	10	80000	10	80000	10	81034	61	395	5228	0	85457	697	12	878	46	6945	86429	740	122	5297	5200	49	6	3	0	5020	1	15	0	1	1	29513	28	80072	564	535	111	80000	80010	29230	29520	29547	29674	29591
160024	29628	221	3	3	3	0	0	7307	0	765	1	0	0	616	124	256	29356	753	678	1736	2058	2320	25	160076	80079	80000	80010	80000	400332	1307477	0	1	78	49	26295	29510	29762	9510	0	3	9672	160010	80020	80000	80020	80000	29372	35	1	1	80021	10	9	27	10	80000	10	80000	10	80958	52	427	6260	0	85969	641	11	889	42	5641	86439	872	128	5330	5256	53	0	3	0	5020	1	25	0	1	1	29458	26	80085	595	556	104	80000	80010	29700	29527	29662	29809	29741
160024	29449	222	4	0	0	1	0	7035	0	843	1	0	0	536	96	92	29651	786	689	2129	2133	2153	25	160084	80068	80000	80010	80000	400296	1310611	0	0	72	49	26425	29604	29447	9321	0	3	9488	160010	80020	80000	80020	80000	29592	35	1	1	80021	10	9	22	10	80000	10	80000	10	80933	66	329	5707	0	86215	599	11	915	90	5380	86312	815	123	5439	4915	70	0	6	0	5020	1	16	0	1	1	29592	41	80057	527	525	114	80000	80010	29478	29711	29464	29619	29653
160024	29540	222	4	0	0	0	0	7180	0	848	1	0	0	608	114	96	29537	846	614	1825	1940	2348	25	160074	80070	80000	80010	80000	400351	1303260	0	0	68	49	26448	29689	29714	9623	0	3	9496	160010	80020	80000	80020	80000	29533	35	1	1	80021	10	9	27	10	80000	10	80000	10	80884	17	346	5266	0	85260	631	11	930	34	5950	86113	736	128	5569	4977	0	3	9	0	5020	1	16	0	1	1	29889	34	80060	506	486	108	80000	80010	29415	29402	29722	29733	29588
160024	29475	222	2	0	0	0	0	6991	0	802	1	0	0	688	118	228	29455	805	612	1873	2037	2083	25	160068	80081	80000	80010	80000	400336	1307322	0	0	64	49	26515	29363	29551	9655	0	3	9604	160010	80020	80000	80020	80000	29583	35	1	1	80021	10	9	51	10	80000	10	80000	10	80897	28	352	5566	0	85708	600	13	890	26	5504	85797	767	143	5027	5270	19	0	5	0	5020	1	16	0	1	1	29549	20	80073	581	510	105	80000	80010	29500	29445	29481	29325	29498
160024	29576	220	2	0	0	0	0	7575	0	880	1	0	0	664	111	216	29462	776	671	1626	1808	2117	25	160072	80066	80000	80010	80000	400333	1297606	0	0	68	49	26316	29413	29438	9434	0	3	9423	160010	80020	80000	80020	80000	29330	35	1	1	80021	10	9	35	10	80000	10	80000	10	80960	53	411	5162	0	85573	627	16	916	34	5897	86876	675	132	5685	4738	52	3	3	0	5020	1	16	0	1	1	29756	40	80070	526	483	107	80000	80010	29479	29652	29475	29765	29178

LDR (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations