Firestorm: LDRSH (unsigned offset, 64-bit) measurements

Code:

  ldrsh x0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	1	1	0	0	65	1	0	1	366	2	18	18	16	25	1000	1000	1000	15604	1	399	398	221	3	256	1000	1000	1000	381	81	1	1	1001	1000	1000	1	1019	20	42	1057	0	0	0	21	1038	6	0	19	42	19	1	73	2	16	2	2	396	9	9	2	1000	383	399	400	382	382
1004	381	3	1	1	0	0	65	0	0	0	384	2	18	18	59	25	1000	1000	1000	15362	0	381	382	221	3	257	1000	1000	1000	381	81	1	1	1001	1000	1000	0	1020	20	42	1066	1	0	0	59	1037	0	1	19	42	19	1	73	2	16	2	2	396	9	0	2	1000	400	382	400	382	400
1004	399	2	1	0	0	0	65	0	0	0	384	2	0	18	16	25	1000	1000	1000	15375	1	382	381	221	3	256	1000	1000	1000	399	82	1	1	1001	1000	1000	0	1021	20	40	1057	0	0	0	21	1038	0	1	57	42	19	0	73	2	16	2	2	379	9	0	2	1000	400	399	400	400	400
1004	381	3	1	0	1	0	65	0	0	2	366	0	18	0	1	25	1000	1000	1000	15318	0	381	399	222	3	257	1000	1000	1000	398	81	1	1	1001	1000	1000	1	1019	19	42	1019	0	0	1	21	1037	6	1	19	42	19	0	73	2	16	2	2	395	9	9	2	1000	400	383	399	400	383
1004	382	2	1	0	0	0	21	0	0	3	383	2	18	0	16	25	1000	1000	1000	15328	0	382	399	221	3	257	1000	1000	1000	381	64	1	1	1001	1000	1000	0	1021	20	42	1057	0	0	0	59	1038	6	0	19	42	19	1	73	2	16	2	2	396	0	9	2	1000	400	401	382	410	383
1004	398	3	1	1	1	0	65	1	0	3	384	2	0	18	20	25	1000	1000	1000	14456	0	399	399	221	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	20	42	1019	0	0	0	59	1038	0	1	57	0	19	0	73	2	16	2	2	396	9	9	2	1000	400	382	382	382	400
1004	399	3	1	0	1	0	65	0	0	2	385	0	0	0	16	25	1000	1000	1000	15320	0	399	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	20	42	1057	0	0	0	59	1038	6	1	57	42	19	0	73	2	16	2	2	378	9	9	2	1000	399	382	400	400	400
1004	399	3	1	0	0	0	65	0	0	2	384	0	18	18	16	25	1000	1000	1000	15362	0	408	398	221	3	242	1000	1000	1000	398	64	1	1	1001	1000	1000	0	1020	19	42	1019	1	0	0	21	1000	6	1	57	0	19	1	73	2	16	2	2	395	9	9	0	1000	399	400	399	400	383
1004	398	2	1	0	0	0	66	1	0	0	383	0	0	18	16	25	1000	1000	1000	14533	0	399	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	19	0	1058	1	1	0	60	1038	6	0	56	42	19	0	73	2	16	2	2	395	9	9	2	1000	400	400	399	400	383
1004	398	3	1	1	0	1	21	0	0	3	384	0	18	18	1	25	1000	1000	1000	15357	0	398	400	221	3	257	1000	1000	1000	381	64	1	1	1001	1000	1000	0	1020	20	0	1057	0	0	0	21	1038	0	0	57	0	19	0	73	2	16	2	2	395	9	9	2	1000	400	399	400	401	400

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70052	525	0	0	2	0	1	1	1	0	1	70045	69791	59719	25	40104	30106	10002	30100	10000	616095	3342686	0	49	66980	0	70060	70078	64658	3	64963	40100	30200	10000	60200	10000	70057	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	1	10001	0	1	1	10000	1	1	1	1	1	2610	2	71	1	1	69820	30006	10	10	10	10000	30100	70061	70061	70042	70061	70042
40204	70057	525	1	1	1	0	0	0	1	0	0	70039	69764	59713	25	40104	30103	10001	30100	10000	616041	3341470	0	49	66974	0	70054	70054	64650	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10003	1	0	1	0	0	2610	1	71	1	1	69817	30003	10	0	0	10000	30100	70055	70036	70060	70036	70036
40204	70054	524	0	0	0	0	0	0	1	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616175	3342398	1	49	66971	0	70054	70051	64647	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	2610	1	71	1	1	69814	30003	10	10	13	10000	30100	70036	70055	70055	70052	70052
40204	70051	525	0	0	0	0	0	0	1	0	0	70020	69785	59713	25	40104	30103	10001	30100	10000	616175	3341470	1	49	66955	0	70054	70035	64631	11	65104	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10001	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69817	30003	10	10	13	10000	30100	70055	70055	70052	70052	70055
40204	70054	524	0	0	0	0	0	0	1	0	0	70039	69785	59713	25	40104	30103	10001	30255	10000	616041	3342398	0	49	66974	0	70035	70054	64631	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2610	1	71	1	1	69817	30003	0	10	13	10000	30100	70036	70055	70036	70055	70036
40204	70051	524	0	0	0	0	0	0	1	0	0	70020	69782	59713	25	40100	30103	10001	30100	10000	616175	3342398	0	49	66955	0	70054	70035	64631	3	64938	40100	30398	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2610	1	71	1	1	69798	30003	10	0	0	10000	30100	70055	70055	70055	70055	70055
40204	70054	524	0	0	0	0	0	0	1	0	0	70020	69785	59695	25	40104	30100	10001	30100	10000	616175	3342254	1	49	67030	0	70054	70054	64650	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30009	10	13	0	10000	30100	70036	70052	70052	70055	70052
40204	70188	524	0	0	0	0	0	0	13	1	0	70036	69764	59713	25	40104	30103	10000	30100	10000	616175	3342398	1	49	66974	0	70035	70051	64650	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69798	30000	10	13	0	10000	30100	70055	70055	70055	70055	70052
40204	70054	524	0	0	0	0	0	0	1	1	0	70020	69785	59713	25	40104	30100	10001	30100	10000	616175	3342398	1	49	66974	0	70054	70054	64650	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10001	0	0	3	10000	1	0	1	0	0	2610	1	71	1	1	69817	30003	10	10	13	10000	30100	70055	70060	70055	70055	70036
40204	70054	525	0	0	0	0	1	0	1	1	0	70045	69764	59713	25	40100	30103	10001	30100	10000	616086	3342398	1	49	66971	0	70051	70054	64650	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69817	30000	10	0	13	10000	30100	70055	70055	70055	70036	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	524	1	1	1	0	0	2	1	0	1	70042	69785	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66980	70060	70057	64678	0	3	64985	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	2	1	10001	0	0	0	1	10000	1	1	1	1	1	0	2520	5	71	1	1	69820	30003	10	10	10	10000	30010	70059	70061	70061	70058	70058
40024	70057	525	1	1	0	0	0	2	0	0	1	70045	69777	59719	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66980	70060	70057	64675	0	3	64985	40010	30347	10055	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	0	10001	0	0	0	1	10000	1	1	1	1	2	0	2520	2	71	1	1	69823	30003	13	10	10	10000	30010	70061	70061	70058	70058	70061
40024	70041	525	1	1	1	0	0	2	1	0	1	70042	69702	59716	25	40018	30016	10002	30010	10000	617072	3342542	1	49	66977	70060	70060	64675	0	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	1	1	10002	0	0	1	1	10000	1	1	1	1	1	0	2520	1	71	1	1	69804	30003	0	10	0	10000	30010	70058	70058	70061	70099	70058
40024	70057	524	1	1	0	0	0	2	0	0	1	70042	69702	59716	25	40018	30013	10001	30010	10000	617072	3342686	1	49	66977	70057	70057	64675	0	3	64966	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	1	10002	0	0	2	1	10000	1	1	1	1	1	0	2520	1	71	1	1	69823	30006	13	10	13	10000	30010	70059	70061	70058	70058	70058
40024	70060	525	1	0	1	0	0	2	1	0	0	70045	69784	59716	25	40018	30016	10002	30010	10000	617072	3342542	1	49	66977	70060	70060	64678	0	3	64982	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	3	0	10001	0	0	1	1	10000	0	1	1	1	1	0	2520	1	71	2	2	69820	30003	10	10	0	10000	30010	70066	70058	70058	70058	70042
40024	70041	525	1	1	1	0	0	2	1	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617072	3342542	1	49	66977	70057	70060	64678	0	3	64982	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	0	1	10000	1	1	1	1	1	0	2520	1	71	1	1	69823	30006	10	10	10	10000	30010	70066	70042	70058	70058	70061
40024	70057	524	1	1	0	0	0	2	0	0	0	70045	69783	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	70041	70060	64678	0	3	64985	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	2	1	10001	0	0	1	1	10000	1	1	0	1	0	0	2520	1	71	1	1	69823	30006	13	13	10	10000	30010	70061	70061	70061	70061	70058
40024	70060	524	1	0	0	0	0	2	1	0	0	70045	69784	59719	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	70057	70057	64659	0	3	64982	40010	30020	10065	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	1	4	10000	1	1	1	1	1	0	2520	2	71	1	1	69820	30003	13	10	11	10000	30010	70125	70065	70061	70058	70058
40024	70057	524	1	0	0	0	0	2	0	0	1	70042	69781	59769	25	40018	30016	10002	30010	10000	617072	3342686	1	49	66961	70041	70057	64675	0	3	64966	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	1	1	10002	0	1	1	1	10000	1	1	1	1	1	0	2520	1	71	1	1	69823	30006	10	0	13	10000	30010	70060	70061	70042	70058	70061
40024	70060	524	1	0	0	0	0	2	1	0	0	70045	69702	59716	25	40018	30013	10001	30010	10000	617045	3342686	1	49	66961	70041	70060	64675	0	3	64982	40010	30020	10000	60020	10000	70043	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	1	0	1	10000	0	1	0	1	0	0	2520	1	71	1	1	69804	30006	10	10	13	10000	30010	70061	70061	70058	70058	70061

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	1	0	0	0	21	0	0	3	26725	2	7	7	20	25	80100	100	80000	100	80000	500	1166758	0	49	23656	0	26737	26736	16659	3	16694	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80022	20	43	0	80059	1	0	1	61	80040	6	1	59	0	19	2	5110	1	16	1	1	26789	13	13	5	80000	100	26738	26715	26737	26737	26737
80204	26736	200	1	1	0	1	0	0	67	0	0	3	26721	3	7	9	20	25	80100	100	80000	100	80000	500	1167224	0	49	23657	0	26715	26736	16659	3	16694	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	21	43	0	80019	0	0	2	61	80040	6	1	19	43	19	0	5110	1	16	1	1	26739	13	13	5	80000	100	26944	26747	26737	26737	26737
80204	26736	200	1	1	0	0	0	0	66	0	0	2	26721	3	7	7	20	25	80100	100	80000	100	80000	500	1164560	0	49	23656	0	26714	26736	16637	3	16695	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	19	43	0	80058	1	0	1	60	80000	6	1	59	43	19	0	5110	1	16	1	1	26739	13	13	5	80000	100	26738	26738	26716	26737	26737
80204	26736	200	1	0	0	0	0	0	67	0	0	3	26721	3	7	7	20	25	80100	100	80000	100	80000	500	1167101	1	49	23656	0	26736	26736	16637	3	16695	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	0	0	80059	1	0	1	38	80000	6	1	39	44	0	0	5110	1	16	1	1	26796	10	10	7	80000	100	26732	26728	26708	26728	26732
80204	26731	200	0	0	0	0	0	0	44	1	0	1	26712	2	1	1	19	25	80100	100	80000	100	80000	500	1165556	0	49	23651	0	26727	26731	16650	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	0	80168	0	2	0	0	80038	6	1	39	44	0	0	5110	1	16	1	1	26778	14	14	4	80000	100	26708	26708	26728	26732	26732
80204	26727	200	0	0	0	0	0	0	45	0	0	1	26716	2	0	1	19	25	80100	100	80000	100	80000	500	1167127	1	49	23627	0	26727	26727	16630	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	0	80038	0	0	0	38	80038	6	1	39	44	0	0	5110	1	16	1	1	26712	14	10	4	80000	100	26708	26708	26732	26728	26732
80204	26732	200	0	0	0	0	0	0	44	0	0	1	26716	2	1	12	19	25	80100	100	80000	100	80000	500	1167231	1	49	23651	0	26727	26707	16650	3	16685	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	0	38	80039	6	1	39	44	0	0	5110	1	16	1	1	26734	14	0	7	80000	100	26728	26708	26708	26728	26708
80204	26707	200	0	0	0	0	0	0	45	0	0	1	26712	2	1	0	16	25	80100	100	80000	100	80000	500	1168312	1	49	23651	0	26731	26731	16654	3	16689	80100	200	80000	200	80000	26731	80	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	0	80038	0	0	0	38	80038	6	1	0	44	0	0	5110	1	16	1	1	26734	14	10	7	80000	100	26732	26728	26728	26732	26728
80204	26707	200	0	0	0	0	0	0	0	0	0	0	26712	2	1	12	19	25	80100	100	80000	100	80000	500	1167127	1	49	23651	0	26731	26731	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	0	38	80038	6	1	39	44	0	0	5110	1	16	1	1	26734	14	10	7	80000	100	26736	26728	26728	26728	26732
80204	26731	200	0	0	0	0	0	0	0	0	0	1	26716	2	12	1	19	25	80100	100	80000	100	80000	500	1165556	1	49	23651	0	26727	26731	16650	3	16689	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	0	80038	0	0	0	38	80038	6	1	39	44	0	0	5110	1	16	1	1	26728	10	10	0	80000	100	26728	26728	26728	26728	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	200	1	0	0	0	41	0	0	1	26696	2	0	0	0	25	80010	10	80000	10	80000	50	1166750	1	49	23647	26722	26722	16667	3	16688	80010	20	80000	20	80000	26788	71	3	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80035	0	1	35	80000	6	0	35	0	0	5020	3	16	2	2	26739	10	6	2	80000	10	26709	26723	26728	26709	26709
80024	26708	200	0	0	0	0	41	0	0	1	26707	0	12	18	0	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26722	26722	16667	3	16702	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	0	0	80000	6	1	35	39	0	5020	2	16	2	2	26735	10	0	0	80000	10	26821	26723	26723	26723	26723
80024	26708	200	0	0	0	0	45	1	0	0	26713	2	0	18	16	25	80010	10	80000	10	80000	50	1166750	1	49	23642	26722	26722	16672	3	16688	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	0	35	80000	0	1	0	39	0	5020	2	16	2	2	26728	6	6	0	80000	10	26728	26709	26728	26723	26723
80024	26708	201	0	0	0	0	0	0	0	0	26707	0	0	0	16	25	80010	10	80000	10	80000	50	1166896	1	49	23628	26722	26708	16672	3	16688	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80035	0	0	35	80035	0	1	35	0	0	5020	2	16	2	2	26724	6	6	2	80000	10	26709	26709	26709	26723	26709
80024	26727	200	0	0	0	0	41	1	0	0	26713	0	0	12	12	25	80010	10	80000	10	80000	50	1166750	1	49	23642	26708	26728	16667	3	16688	80010	20	80000	20	80000	26722	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	0	35	80039	6	0	0	0	0	5020	2	16	2	2	26708	0	6	0	80000	10	26729	26709	26709	26709	26709
80024	26722	200	0	0	0	0	0	0	0	1	26707	3	0	18	0	25	80010	10	80000	10	80000	50	1172240	1	49	23807	26722	26722	16652	3	16702	80010	20	80000	20	80000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	35	80000	6	1	0	39	0	5020	2	16	2	2	26724	0	10	4	80000	10	26728	26729	26723	26723	26723
80024	26708	200	0	0	0	0	0	1	0	0	26707	2	0	12	0	25	80010	10	80000	10	80000	50	1166750	0	49	23628	26722	26722	16667	3	16702	80010	20	80000	20	80000	26722	72	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	0	0	80000	0	0	35	39	0	5020	2	16	2	2	26875	0	0	0	80000	10	26723	26727	26723	26723	26709
80024	26708	200	0	0	0	0	45	0	0	1	26712	2	12	18	16	25	80010	10	80000	10	80000	50	1166750	0	49	23642	26708	26728	16652	3	16702	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	39	80036	6	0	35	0	0	5020	2	16	2	3	26721	6	6	2	80000	10	26709	26729	26723	26723	26709
80024	26708	200	1	0	0	0	0	1	0	0	26712	0	18	0	12	25	80010	10	80000	10	80000	50	1166750	0	49	23642	26722	26722	16668	3	16702	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	0	35	80035	6	0	35	0	0	5020	2	16	2	3	26724	0	6	2	80000	10	26729	26709	26709	26723	26723
80024	26708	200	0	0	0	0	41	0	0	2	26693	0	0	0	11	25	80010	10	80000	10	80000	50	1167605	1	49	23628	26727	26727	16667	3	16707	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	0	39	80039	6	1	0	43	0	5020	2	16	2	3	26709	6	10	2	80000	10	26723	26709	26728	26723	26723

LDRSH (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations