Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STEORLB

Test 1: uops

Code:

  steorlb w0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.006

Integer unit issues: 1.006

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e1f22243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6061696a6d6emap rewind (75)map stall (76)dispatch uop (78)79map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
730053311924712001810110021106137327850020925300510052000100020001108217051500492993732655329193123000010002000200040003275026081171001100010001200340210061001018200661202216144122422839639235512280941364440244743323981006167181487414710200010003291632656330723263932882
730043276724511511211110051006117329670020603300610072000100020001095916952100492979032708329113123000010002000200040003282925981171001100010000200330210051001026200241322216409125161834939777452300139144442214739324321005170451477114820200010003264132936327583285532500
730043288624611611210110071005983326930120702300610042000100020001108916856800492980332699329363133000010002000200040003279725801171001100010000200442310051001027200451002115997120342847340013402263839634444154140323791004167871464515572200010003276432767326643253232755
730043262024611401600110071005899330640120844300610072000100020001099816907500492949932884328513133000010002000200040003272926141171001100010000200222010071001026200331232216252120521843041118402287337844446114640323531008162181481415264200010003287732740325703284532868
730043319924611811410010101105960327171120759300810082000100020001114917038316492979932682326663103000010002000200040003295725921171001100010001200333210051001008200461302116449119351854338653432303139034446164541324911005170391499516061200010003284433141326033287433073
730043300624811301601010061005910328150020834300810062000100020001095316989900492967532837329453133000010002000200040003277526071171001100010000200320310081001015200461302216081118523830639025432282038674441174440323711006173251502615618200010003302632829329373287532876
730043297824511701310110081006000328121120679300510072000100020001102617026906492993132607327903123000010002000200040003264926061171001100010000200440310071001026200581332016415115532830739479382301339774442184444323831006166181572415286200010003309832702326603282232840
730043307724611311900010071005956327160020612300610062000100020001116016921606492982832727329703103000010002000200040003300125761171001100010000200630310051001126200681332016198120721843340257442280339064437174351324571006167461438315372200010003265232847327813269132722
730043262924711111400010091005728327230020473300910052000100020001100217006800492975532809330513123000010002000200040003299426111171001100010000200433010091001006200361032116161118093836838677382272638804446114440324671008172021514515480200010003290932841328283270032596
730043290024501701400010060006075327440120687300610062000100020001110416908710492965832636328463133000010002000200040003298726091171001100010000200002210021000002200520220016094117222826538314402290439314440143942323731005172311467215134200010003261932836328483299432919

Test 2: throughput

Code:

  steorlb w0, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f181e1f202223293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)67696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40206700745251002020511010331001207005934917115639925403442040420000201002000020447083320896108496698970033700696450536502440100202002000030200400007006963112020110099010010000101001000011002006217100441987210069100101033246920060143115817315001310116116985420232111020000201007007070070700707007070070
4020470069525110200050579251002307005835811105751925404092038320000201002000020446203320439121496699370037700736451136503240388202002000030200400007007371112020110099010010000101001000001002004526211611987210088100212440060200681272361321101310116116991320253101020000201007006870070700707007070070
402047006952511000005049449100110700503281110583412540353202602000020100200002045307332178711849669907003370069645033650084010020200200003020040000700706311202011009935110010000101001000001002003511336419871100711001942604234200691263411301001310116116985620394101020000201007007070070700707007070070
4020470069524100100050602421001007005237861058130254053820458200002010020000204478133219411044966989700337006964507365027401002020020156302004000070069631120201100990100100001010010000010020033373501987110062100164032263420061023335981201310116116985620173101020000201007007070070700707007070070
40204700695251000000509032810013287005449141957931254035120385200002010020000204517533214816049669977003370069645073650274010020200200003020040000700696311202011009901001000010100100000100200362965819871100681000232372435200531324311301101310116116985620201101020000201007007070070700707007070070
40204700695251100000506434410247070035329828582942540521205182000020250200002044945332133210349669897003370069645073650254010020200200003020040000700696311202011009901001000010100100000100200244111541987010083100142124642200531416301331001310117116985620293101020000201007007070070700707007070070
40204700645251011000564053200011287005441015165881825404162026620000201002000020446713320084124496698970033700696450736502740100202002000030200400007006969112020110099010010000101001000001002003511494619871100901000443383038200712293411501101310117116985620230101320000201007007070070700707007070070
4020470069524110000050553371007127005231817115852025403152037820000201002000020451543320669208496698970033700696450736502740100202002000030200400007006963112020110099010010000101001000011002002531493919871100691000411423038200622333682961101310116116985620262101020000201007007070070700707007170070
40204700695251101000508937000607005417810958522254030220247200002010020000204484133216352114966989700337006964507365027401002020020000302004000070069631120201100990100100001010010000010020028011032198661004110001315463420062131315910001310116116985620418101020000201007007070065700707007070070
402047006952500000005058232100107005409202258612254034920344200002010020000204497333220302134966989700277006464507365021401002020020000302004000070069631120201100990100100001010010000010020028274491987110058100021236383620056127623571001310116116985520265131020000201007007070070700707007070070

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f20222324293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
400267945359110022022248095203224100018082464241710665551354024520581216802238721932224811836759510222497492478021780247139716972933417302002020000300204030470069641120021109010100001001010000010200391316864198721017210008612922432004412883711314212715162369856231109920000200108107381544820578186770070
4002470069547123000182077461679331000907960228197569882540213203562031522384228982044686332211012974978958834068101967986365049400102002020000300204101670080611120021109350101000010010100001102004818744198701014610018114136832005912984014913012713163369843202529920000200107057770070700707005770070
40024700695251101000050438260010160700543111113575442540573202662000020010200002044369332189001764966989700297006964529365049400102002020000300204030170069581120021109010100001001010000010200471495432026810138100084823524522005113184111213212713163269856202519920000200107007070070705607007070070
40024700695251001000050668310100190700542911113578792540437207672000020603200002044389332089101204966989700297006964516365049400102002020000300204000070069601120021109010100001001010000010200391411246198681012110018412363046200410308379513112712162369843203459920000200107007070070700577005770070
40024700695241000000050538490100110700541719125736725407322066920000200102000020441623321107082496698970029700696452936504940010200202000030020403047006966112002110901010000100101000001020036167753198721012110008531513646200531138386014212913164369856203069920000200107007070573700817007070081
400247006952510000000504672001002020700541918115757525402182036420105200102000020445713320824183496698970029700696452936504940010200202000030020400007006965112002110901010000100101000001020033177740198681013810008461281242200401158409513112713253369856205849920000200107007070070700707007070070
40024700695251101000050497220100170700541715115787725406462053720000201612000020439883320651116949669897002970069645293650494001020020200003002040000700696411200211090101000010010100000102003414594719872101411000855145245083200691328385914112713163369856202100920000200107007070070700707007070070
4002470069525110100005069924010083270054231365833925403262042220000200102000020436803320975112349669897002970069645163650364001020020200003002040000700696711200211090101000010010100000102004320112461987210118100223812624632006213583411413112713163269856202749920000200107005770070700707007070070
40024700695251100000050789320100160700542317358326254021220261200002060420138204384533220471210496698970029700696452936504940010200202000030020400007006967112002110901010000100101000011020061161144319872101281002252672452200661338437613012713163269843203319020000200107005770070700707007070057
40024700695241100000050448250100190700412421210580212540311202582000020010200002043685332062002514966989700297006964529365049400102002020000300204000070069671120021109010100001001010000010200491495521987010129100085015316622017413184916613012712243369856201849920000200107007070070700707005770070

Test 3: throughput

Code:

  steorlb w0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0126

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3020522017116491000000026923000122011866020204625508792815523219102002028686702021052185914504921705322012822015121548872163203010017982232102032000520206400092201568861110201100991001000010010000010020000029271601000001701837145171860031111720984001633219441157273756612000010100220122220153220156220109220120
3020422011116480000000027598000022011066112024092550865274322309310100200008381402105253201489492170352201332201662154676216348301001965188410200200002029240000220133936111020110099100100001001000001002000002326055100010172963691317225022331117181012231614219369187273264002000010100220112220118220148220140220120
3020422012516490000110026942100122013412511202398255081827937230011010020000868246810523687151349217033220145220161215433621633330100193019421020320005202064000922014788011102011009910010000100100000100200000252728610000016814364231692010311117201070641643219417203276546602000010100220120220134220187220124220128
30204220163164900000000276510100220118610020192725506852707422873101002000087761441052599614474921707522011522016321546762163213010019101805102032000520206400092201198651110201100991001000010010000010020000333326796100010170133693017078113311117181045001644219433195271846602000010100220138220136220169220158220142
3020422012116490000000027376001122010886142022042550795281572264410100200008565484105452761475492170692201412201412154276216383301001941177610203200052020640009220115886111020110099100100001001000001002000034282717110000016480364241696400331117181043211644219430151268896902000010100220164220220220165220153220124
30204220119164900000000270300011220116760202042255067927700225601010020000860095410526683143849217045220145220165215472621637930100189619771020320005202064000922016487611102011009910010000100100000100200003019273131000001690937455169420001117201009841634219439112275766602000010100220134220180220177220158220128
30204220123164900000000277720011220140881320250425506922772823191101002000083917741052488915194921703322012322011321546762163253010019682079102032000520206400092201218771110201100991001000010010000010020000020270141000001714837100170050001117201099341613219444178266134002000010100220146220124220171220121220146
3020522012116490000000027285100122012875020285425506972739923285101002000086082051052304314534921704522011922012521552362163443010020402609102032000520206400092201518581110201100991001000010010000010020000302227146100010166883691616833016311117181028041644219439120271786602000010100220144220179220133220126220118
30204220143164900000000265530010220122771320221925506362735523780101002000082860961052683715254921703322011322013521547562163413010020161676102032000520206400092201378901110201100991001000010010000010020000272526718100360173413713317571021331117201074641644219443230278006612000010100220138220176220172220124220166
3020422010116490000000027686101122011857132043752550525272882327110100200008551590105247101532492170532201392201692155316216315301002272194210203200052020640009220111918111020210099100100001001000001002000027222727210000016931372051726600271117201045041614219479138276110602000010100220125220145220227220143220130

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0264

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
30025220166164800000031652100122020230172012462552860327062011910010200001059402410524205013309821718702202352203352153383216535300101371521002020000200204000022027570011100211095012910100001010000110200262736423150010016571215174148321394131310006401528021622219383032691062000010010220244220274220294220232220250
3002422031316501000003141200002203070017201765255286832707200971001020000105689051052513701366492171570220291220257215382321653930010152155100202000020020402172203277171110021109291291010000101000011020025000315471000110215204146221475125310006401513221622219363132671002000010010220296220280220238220230220284
3002422025316490000003154510002201864140200874255286732792200781001020000106418931052313701337492171913220231220263215404321647730010129130100202000020020400002202236921110021109618881010000101000011020000027273155610000002152741503215161031000640152142152221941523271310102000010010220264220232220270220256220280
30024220263165000000031396100022030831312201437255282932783200791001020000106314591052658201360492171650220243220251215381321647830010131134100202000020020400002202436582110021109605351010000101000011020027031273150510001002146541467214630031000640151832162221936923270210102000010010220264220244220252220268220252
300242202131649000000315650101220196301420087725527923279220059100102000010676532105232111133449217163022020922023121533132164183001014411510020200002002040000220257724111002110957545101000010100001102000000273156710001002153541459214961293100065915347216222193430327431002000010010220242220264220258220196220282
300242202411649000000315701000220256101420141325528403283220052100102000010723749105236450137049217191022023122026521538032164873001013112310020200002002040000220263728111002110943405101000010100001102002503127315571000110215674155321520130000064015285216222193690327820102000010010220278220230220262220252220266
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