Firestorm: STRH (register, uxtw) measurements

Code:

  strh w0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	552	4	1	0	1	1	0	18	1	1	537	16	16	5	25	1000	1000	1000	22932	1	558	551	372	3	415	1000	1000	3000	559	560	1	1	1001	1000	1000	1014	15	36	0	0	1016	0	0	18	1002	16	36	14	2	73	2	16	1	1	549	1000	559	559	559	553	554
1004	552	4	1	0	1	0	0	20	1	1	536	16	15	5	25	1000	1000	1000	22908	1	559	552	371	3	410	1000	1000	3000	558	552	1	1	1001	1000	1000	1015	14	36	0	1	1016	0	0	16	1002	16	36	14	1	73	1	16	1	1	549	1000	559	553	553	552	551
1004	560	4	1	0	1	1	0	19	1	1	535	16	16	5	25	1000	1000	1000	22932	0	552	559	365	3	416	1000	1000	3000	552	559	1	1	1001	1000	1000	1016	15	35	0	2	1016	0	2	18	1002	16	36	14	1	73	1	16	1	1	548	1000	560	553	553	551	561
1004	560	4	1	1	0	0	0	19	1	1	546	16	16	2	25	1000	1000	1000	22836	0	560	558	364	3	417	1000	1000	3000	551	559	1	1	1001	1000	1000	1016	14	36	0	1	1016	0	1	17	1002	16	36	14	1	73	1	16	1	1	549	1000	559	553	553	552	551
1004	560	4	1	1	1	1	0	18	0	1	537	16	16	5	25	1000	1000	1000	23340	0	559	552	373	3	410	1000	1000	3000	560	559	1	1	1001	1000	1000	1015	14	36	0	1	1016	0	1	20	1002	16	36	14	2	73	1	16	1	1	548	1000	553	554	553	551	561
1004	558	4	1	0	1	1	0	19	1	1	545	16	16	5	25	1000	1000	1000	22908	0	551	638	365	3	417	1000	1000	3000	552	561	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	2	20	1002	16	36	14	0	73	1	16	1	1	557	1000	554	553	551	562	560
1004	559	4	1	1	1	0	0	21	1	1	538	16	16	5	25	1000	1000	1000	22812	1	552	561	372	3	416	1000	1000	3000	559	550	1	1	1001	1000	1000	1016	16	36	0	1	1016	0	1	18	1002	16	36	14	0	73	1	16	1	1	547	1000	553	553	552	561	562
1004	559	4	1	0	0	1	0	18	1	1	543	16	16	2	25	1000	1000	1000	23316	1	552	559	365	3	417	1000	1000	3000	552	560	1	1	1001	1000	1000	1015	14	36	0	1	1016	0	1	16	1002	16	36	14	0	73	1	16	1	1	557	1000	553	551	561	558	559
1004	552	4	1	1	1	0	0	19	1	1	535	16	16	5	25	1000	1000	1000	22908	1	559	551	371	3	408	1000	1000	3000	558	553	1	1	1001	1000	1000	1015	15	36	0	1	1016	0	1	18	1002	16	36	14	0	73	1	16	1	1	548	1000	560	553	553	551	561
1004	560	4	1	0	1	1	0	19	1	1	546	16	16	2	25	1000	1000	1000	22908	1	558	550	372	3	418	1000	1000	3000	559	552	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	1	17	1002	16	36	14	2	73	1	16	1	1	549	1000	559	559	559	554	554

Count: 8

Code:

  strh w0, [x6, w7, uxtw]
  strh w0, [x6, w7, uxtw]
  strh w0, [x6, w7, uxtw]
  strh w0, [x6, w7, uxtw]
  strh w0, [x6, w7, uxtw]
  strh w0, [x6, w7, uxtw]
  strh w0, [x6, w7, uxtw]
  strh w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	498	3	1	0	40027	16	16	0	25	80100	100	80000	100	80337	500	1839474	49	36963	0	40042	40042	29964	7	29992	80106	200	80016	200	240048	40042	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	0	42	0	1	1	1	5118	0	16	0	0	40039	0	80000	100	40043	40043	40041	40044	40044
80204	40043	300	0	87	0	1	0	40039	0	16	0	25	80100	100	80000	100	80006	500	1840031	49	36960	0	40040	40040	29959	7	29992	80107	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	80000	2	0	0	1	1	1	5118	0	16	0	0	40039	0	80000	100	40044	40041	40043	40044	40043
80204	40043	300	0	66	3	1	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839474	49	36962	0	40042	40042	29964	7	29994	80106	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80000	1	2	80000	0	0	0	1	1	1	5118	0	16	0	0	40037	0	80000	100	40043	40043	40041	40043	40055
80204	40040	300	0	6	3	0	0	40027	0	16	0	25	80100	100	80000	100	80006	500	1839378	49	36962	0	40042	40042	29962	7	29992	80106	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	2	42	0	1	1	1	5118	0	16	0	0	40039	0	80000	100	40043	40043	40043	40041	40043
80204	40042	300	0	36	3	0	0	40039	16	16	0	25	80100	100	80000	100	80006	500	1839378	49	36962	0	40040	40054	29959	7	29996	80107	200	80016	200	240048	40043	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	5	80002	2	42	0	1	1	1	5118	0	16	0	0	40039	0	80000	100	40043	40044	40041	40043	40044
80204	40040	299	1	33	0	1	0	40028	16	16	1	25	80100	100	80000	100	80006	500	1839503	49	36960	0	40040	40040	29962	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	1	80002	0	0	80002	2	42	0	1	1	1	5118	0	16	0	0	40040	0	80000	100	40044	40044	40041	40041	40043
80204	40042	300	0	0	3	1	0	40027	16	0	1	25	80100	100	80000	100	80006	500	1839474	49	36963	0	40043	40040	29962	7	29994	80106	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80000	0	5	80002	0	42	0	1	1	1	5118	0	16	0	0	40040	0	80000	100	40044	40041	40043	40044	40041
80204	40042	300	0	6	0	1	0	40027	0	16	1	25	80100	100	80000	100	80006	500	1839474	49	36962	0	40040	40042	29959	7	29994	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80000	0	3	80000	2	42	0	1	1	1	5118	0	16	0	0	40039	0	80000	100	40043	40043	40043	40043	40043
80204	40040	300	0	6	3	1	0	40027	0	16	0	25	80100	100	80000	100	80006	500	1839474	49	36962	0	40040	40042	29961	7	29994	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	2	42	0	1	1	1	5118	0	16	0	0	40039	5	80000	100	40041	40043	40043	40043	40041
80204	40040	300	0	273	0	1	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839474	49	36962	0	40042	40042	29962	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	80002	0	42	0	1	1	1	5118	0	16	0	0	40039	0	80000	100	40043	40041	40043	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40052	300	1	1	1	0	0	21	3	1	0	0	0	40025	16	16	1	25	80010	10	80000	10	80000	50	1839472	0	0	0	49	36962	40040	40042	29990	3	30031	80010	20	80000	20	240000	40055	40063	1	1	80021	10	9	10	80000	10	80000	10	80015	16	44	0	2	80016	0	2	16	80002	16	44	14	0	5020	0	0	14	16	14	10	40037	80000	10	40041	40041	40043	40043	40043
80024	40042	300	0	0	0	0	0	12	19	0	0	0	1	40032	16	16	2	25	80010	10	80000	10	80000	50	1840004	0	0	0	49	36974	40051	40054	29977	3	30020	80010	20	80000	20	240000	40040	40054	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	2	80000	0	0	0	0	5020	0	0	16	16	11	15	40044	80000	10	40055	40064	40055	40053	40054
80024	40047	300	1	0	0	0	1	63	3	0	0	0	1	40039	16	0	1	25	80010	10	80000	10	80000	50	1839908	0	0	0	49	36974	40054	40054	29987	3	30034	80010	20	80000	20	240000	40051	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	14	44	0	0	80014	0	0	18	80002	16	0	14	2	5020	0	0	13	16	15	16	40051	80000	10	40048	40055	40055	40048	40052
80024	40055	300	1	0	1	0	1	18	19	0	0	0	1	40048	16	16	3	25	80010	10	80000	10	80000	50	1840460	0	0	0	49	36974	40052	40054	29988	3	30034	80010	20	80000	20	240000	40052	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	0	0	0	80016	0	1	17	80002	16	44	14	1	5020	0	0	14	16	15	12	40048	80000	10	40048	40055	40064	40055	40056
80024	40047	300	1	1	1	0	1	6	14	1	0	0	1	40039	16	0	4	25	80010	10	80000	10	80000	50	1839884	0	0	0	49	36975	40054	40054	29990	3	30034	80118	20	80000	20	240000	40047	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	16	44	0	0	80016	0	1	14	80002	16	44	14	0	5020	0	0	15	16	15	13	40051	80000	10	40054	40055	40055	40064	40052
80024	40055	300	1	1	1	0	0	12	14	1	0	0	1	40039	16	16	1	25	80010	10	80000	10	80000	50	1840004	0	0	0	49	36968	40054	40054	29989	3	30043	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	15	44	0	1	80016	1	0	16	80000	16	0	14	1	5020	0	0	12	16	11	11	40044	80000	10	40055	40053	40055	40052	40055
80024	40052	300	1	0	1	0	1	453	22	1	0	0	1	40039	16	16	0	25	80010	10	80000	10	80000	50	1839956	0	0	0	49	36983	40054	40047	29989	3	30032	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	15	44	0	1	80016	0	0	17	80002	14	44	14	1	5020	0	0	13	16	13	16	40060	80000	10	40056	40048	40055	40179	40055
80024	40054	299	1	1	0	0	1	267	3	1	0	0	2	40217	16	16	1	25	80010	10	80000	10	80000	50	1839692	0	0	0	49	36967	40054	40054	29990	20	30034	80010	20	80000	20	240000	40051	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	14	44	0	0	80014	0	0	21	80002	16	44	14	1	5020	0	0	14	16	13	10	40039	80000	10	40041	40043	40043	40043	40043
80024	40040	300	0	0	0	0	0	30	14	1	0	0	1	40039	0	16	2	25	80010	10	80000	10	80000	50	1840004	0	0	0	49	36974	40051	40054	29977	3	30020	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	1	0	2	80000	0	42	0	0	5020	0	0	12	16	12	14	40044	80000	10	40048	40048	40052	40055	40064
80024	40054	300	1	0	1	0	1	519	3	0	0	0	0	40027	16	0	1	25	80010	10	80000	10	80000	50	1839352	0	0	0	49	36962	40042	40040	29987	3	30027	80010	20	80000	20	240000	40052	40052	1	1	80021	10	9	10	80000	10	80000	10	80014	15	44	0	1	80016	0	0	16	80002	16	0	14	0	5020	0	0	11	16	11	14	40037	80000	10	40043	40041	40041	40043	40044

STRH (register, uxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations