Firestorm: SUB (sxtb, 64-bit) measurements

Code:

  sub x0, x0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	0	66	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	61	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	2	67	2	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	17	0	0	61	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	0	81	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	3	2	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	61	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	52	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	61	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	0	75	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	2	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	0	61	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	0	61	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	3	3	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	0	61	1000	1735	25	2000	2000	1000	32570	0	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	3	67	2	2	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  sub x0, x0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	61	10000	19803	86	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	21	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	2	19822	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10362	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	3	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	2	87	0	640	2	63	3	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	1	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	2	3	0	640	2	63	2	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	3	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	1	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  sub x0, x1, w0, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	66	10000	19803	25	20100	20100	10100	185342	0	5	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	5	2	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	5	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	710	0	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20129
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	187068	1	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	0	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	5	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	0	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	0	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	0	61	10000	19803	25	20100	20100	10100	185342	0	5	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	5	4	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	99	10000	19803	25	20100	20100	10100	185342	1	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	0	0	1	59	1	1	19791	20000	10100	20177	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	1	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	53	3	710	0	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	160	10000	19803	25	20100	20100	10100	185342	1	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	5	1	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	5	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	710	0	0	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	4	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	3	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20079	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	2	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	1	3	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	1	3	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	441	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	1	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  sub x0, x8, w9, sxtb
  sub x1, x8, w9, sxtb
  sub x2, x8, w9, sxtb
  sub x3, x8, w9, sxtb
  sub x4, x8, w9, sxtb
  sub x5, x8, w9, sxtb
  sub x6, x8, w9, sxtb
  sub x7, x8, w9, sxtb

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26767	200	0	0	0	0	0	0	145	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	22	1	1	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	0	0	0	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	22	1	1	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	0	0	0	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	25	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	1	0	0	0	5110	1	22	1	1	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	0	0	264	440	193	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26845	16618	3	16677	80749	80848	162374	27016	39	6	1	80201	100	99	100	80100	100	4	0	2	1	0	3401	4	5229	1	64	1	1	27020	160000	80100	27019	27020	27075	27081	27080
80204	27016	202	1	0	5	5	669	440	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26788	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	2	5182	1	64	1	1	26966	161120	80100	26726	26788	26726	26726	26726
80204	26725	200	0	0	0	0	669	528	1567	80499	23751	148	161233	161047	81174	181117	1	49	23998	27021	27021	16627	45	16819	81172	81272	162788	27019	39	6	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	22	1	1	26717	160000	80100	26726	26726	26726	26792	26726
80204	26725	200	1	0	0	0	0	0	193	80078	26062	74	160100	160497	80528	177374	1	49	23883	26784	26791	16621	35	16771	80314	81072	161068	26902	39	3	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	54	2	1	26717	160000	80100	26726	26726	26787	26785	26902
80204	27020	202	1	1	1	3	669	440	1674	80488	24587	194	161429	161237	81172	187513	1	49	23995	27078	27076	16625	61	16819	81371	81505	162786	27077	39	7	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	22	1	1	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	0	0	0	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	4	4	4	0	0	2175	0	5207	1	55	1	1	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	0	0	9	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26788	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	22	1	1	26717	160000	80100	26726	26726	26726	26726	26726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26735	200	0	0	103	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	4	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	251	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	4	2	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	631	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	2	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	2	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	2	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23687	0	26771	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	3	0	0	0	5020	0	0	2	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	2	22	2	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	2	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	2	22	0	3	2	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	0	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	2	22	0	2	2	26704	160000	80010	26712	26712	26712	26712	26712

SUB (sxtb, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations