Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CRC32CW

Test 1: uops

Code:

  crc32cw w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004303323006119222510001000100081440140303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
1004303323006119222510001000100081440140303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
1004303322006119222510001000100081440140303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
1004303323006119222510001000100081440040303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
1004303322006119222510001000100081440040303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
10043033220276119222510001000100081440140303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
1004303322006119222510001000100081440040303330332760328911000100020003033380111001100010732162229391000100030343034303430343034
1004303322006119222510001000100081440040303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
1004303323006119222510001000100081440040303330332760328911000100020003033380111001100000732162229391000100030343034303430343034
1004303322006119222510001000100081440040303330332760328911000100020003033380111001100000732163329391000100030343034303430343034

Test 2: Latency 1->2

Code:

  crc32cw w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204300332240006119922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001000710116112993910000101003003430034300343003430034
102043003322500246119922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001000710116112993910000101003003430034300343003430034
10204300332250006119922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001000710116112993910000101003003430034300343003430034
10204300332240006119922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001000710116112993910000101003003430034300343003430034
10204300332250006119922251010010100101008289400492695330033300332861032874110100102002049230033374111020110099100101001000710116112993910000101003007830078300783003430034
102043003322500010319922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001001958710116112993910000101003003430034300343003430034
10204300662250006119922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001000710116112993910000101003003430034300343003430034
102043003322400010319922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001000710116112993910000101003003430034300343003430034
102043003322500126119922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001000710116112997110000101003007830077300343003430034
10204300332250117110319922251010010100101008289400492695330033300332861032874110100102002020030033374111020110099100101001003710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250007261992225100101001010010828490492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250018611992225100101001010010828490492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250030611992225100101001010043828490492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322500156119922251001010010100108284904926953300333003328632328763100101002020020300333801110021109101001010018640216222993910000100103003430034300343003430034
10024300332250012611992225100101001010010828490492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103006930034300343003430034
10024300332250015611992225100101001010010828490492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250015611992225100101001010010828490492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
1002430033225000611992225100101001010010828490492695330033300332863232876310010100202002030033380111002110910100101010640216222993910000100103003430034300343003430034
1002430033225000611992225100101001010010828490492695330033300332863232876310010100202002030033380111002110910100101000640216232997310008100103003430034300343003430078
1002430033225019611992225100101001010044828490492695330077300752863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034

Test 3: Latency 1->3

Code:

  crc32cw w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204300332250004051992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000000710116112993910000101003003430034300343003430034
10204300332250007261992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000400710116112993910000101003003430034300343003430034
10204300332250003461992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000000710116112993910000101003003430034300343003430034
10204300332250002511992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000100710116112993910000101003003430034300343003430034
1020430033225000611992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000200710116112993910000101003003430034300343003430034
10204300332240007261992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000000710116112993910000101003003430034300343003430034
10204300332250007261992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000000710116112993910000101003003430034300343003430034
10204300332250002511992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000030710116112993910000101003003430034300343003430034
1020430033225000611992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000000710116112993910000101003003430034300343003430034
10204300332250007261992225101001010010100828940492695330033300332861032874110100102002020030033374111020110099100101001000030710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250906119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
10024300332330006119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
10024300332250606119922251001010010100108284900492695330033300332863232878010010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
100243003322501808219922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
100243003322501806119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
100243003322502706119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
100243003322409306119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
100243003322401806119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034
1002430033225033526119922251001010010100108284900492695330033300332863232876310010100202012030033380111002110910100101000000640216222993910000100103003430034300343003430034
100243003322501806119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000000640216222993910000100103003430034300343003430034

Test 4: throughput

Count: 8

Code:

  crc32cw w0, w8, w9
  crc32cw w1, w8, w9
  crc32cw w2, w8, w9
  crc32cw w3, w8, w9
  crc32cw w4, w8, w9
  crc32cw w5, w8, w9
  crc32cw w6, w8, w9
  crc32cw w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204800355990000004625801008010080100400500049769558003580035699643699938010080200160200800351641180201100991008010010000000001005110416328003180000801008003680036800368003680036
802048003559900003092404625801008010080100400500049769558003580035699643699938010080200160200800351641180201100991008010010000000000005110316238003180000801008003680036800368003680036
80204800355990000004625801008010080100400500149769558003580035699643699938010080200160200800351641180201100991008010010000000000005110316338003180000801008003680036800368003680036
80204800356000000004625801008010080100400500098769558003580035699643699938010080200160200800351641180201100991008010010000000000005110316328003180000801008003680036800368003680036
80204800356000000004625801008010080100400500049769558003580035699643699938010080200160200800351641180201100991008010010000000000005110216338003180000801008003680036800368003680036
80204800355990000004625801008010080100400500149769558003580035699643699938010080200160200800351641180201100991008010010000000000005110316238003180000801008003680036800368003680036
80204800356000000004625801008010080100400500049769558003580035699643699938010080200160200800351641180201100991008010010000000600005110316328003180000801008003680036800368003680036
80204800355990000004625801008010080100400500049769558003580035699643699938010080200160200800351641180201100991008010010000000000005110216328003180000801008003680036800368003680036
80204800355990000004625801008010080100400500049769558003580035699643699938010080200160200800351641180201100991008010010000000000005110316338003180000801008003680036800368003680036
80204800356000000004625801008010080100400500049769558003580035699643699938010080200160200800351641180201100991008010010000000000005110316338003180000801008003680036800368003680036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800248003559900010004625800108001080010400050049769558003580072699863700158001080020160020800351641180021109108001010000350201617015108003280000800108003680036800368003680036
8002480035600000000052125800108001080010400050049769558003580035699863700158001080020160020800351641180021109108001010000050201016014138003280000800108003680036800368003680036
8002480035599000000052125800108001080010400050049769558003580035699863700158001080020160020800351641180021109108001010000050201216014118003280000800108003680036800368003680081
8002480035600000000071125800108001080034400050049769558003580035699863700158001080020160020800351641180021109108001010000050201216012128003280000800108003680036800368003680036
80024800356000000000462580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000005020141601298003280000800108003680036800368003680036
800248003559900000004625800108001080010400050049769558003580035699863700158001080020160020800351641180021109108001010000050201316014138003280000800108003680036800368003680036
80024800355990000000462580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000005041151609138003280000800108003680036800368003680036
800248003560000000004625800108001080010400050049769558003580035699863700158001080020160020800351641180021109108001010000050201016013168003280000800108003680036800368003680036
800248003560000000004625800108001080010400050049769558003580035699863700158001080020160020800351641180021109108001010000050201516012118003280000800108003680036800368003680036
800248003559900000004625800108001080010400050098769558003580035699863700158001080020160020800351641180021109108001010000050201316015128003280000800108003680036800368003680036