Firestorm: AUTIZA measurements

Code:

  autiza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	3	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	2	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	64	0	104	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	2	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	27	146	5824	25	1000	1000	1000	178330	49	3988	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	1	0	73	3	85	3	4	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1028	1000	1000	7029	870	1	1	1001	1000	1	0	73	3	85	3	2	6789	1000	1000	7030	7030	7030	7030	7030
1004	7069	70	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	4	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autiza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	621	0	1	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	652	0	0	0	0	57	0	0	82	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69934	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	0	82	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	619	0	0	0	0	462	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70054	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	23	10100	70030	70030	70030	70030	70030
10204	70029	652	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	649	0	0	0	0	12	0	0	89	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	1	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	3	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	627	0	0	0	0	39	0	0	103	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	617	0	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	1	0	640	2	79	2	3	69805	10010	2	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	1	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	1	0	0	0	0	640	2	79	3	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	754	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70054	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	3	3	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	131	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	0	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	103	59788	25	10020	10020	10104	1807818	1	49	66949	0	70068	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	3	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70069	621	0	0	0	0	0	0	13527	59662	454	10087	10079	10526	1809395	1	49	66949	0	70029	70029	68502	3	68696	10020	10662	10560	70581	1385	16	1	10021	10	9	10010	0	0	0	4	0	0	972	4	266	5	4	70634	10095	0	10010	71211	71209	71171	71211	71173
10024	70970	686	0	0	0	3300	2288	0	14214	59617	513	10094	10089	10665	1809273	0	49	67892	0	70972	71051	68760	165	69480	10862	11273	11308	70300	1287	2	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  autiza x0
  autiza x1
  autiza x2
  autiza x3
  autiza x4
  autiza x5
  autiza x6
  autiza x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80041	700	0	0	0	0	1	0	0	0	77	25	80200	80200	80200	401000	0	49	76955	3	80035	80080	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	3	0	0	5110	0	2	25	2	2	80025	80100	80100	80082	80036	80036	80171	80036
80204	80035	702	0	0	0	0	0	12	0	0	5780	25	80200	80200	80200	401107	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	2	0	9	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	1	0	0	0	12	0	0	742	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	8	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	3	0	0	5110	0	2	25	2	2	80025	80121	80100	80036	80036	80036	80036	80036
80204	80035	697	0	0	0	0	0	12	0	0	35	25	80200	80200	80200	401107	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	3	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	45	0	0	77	25	80200	80200	80200	401107	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	2	1	80201	100	99	80100	0	0	0	1	0	3	0	0	5110	0	2	25	2	2	80025	80121	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	12	0	0	77	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	2	2	10708	0	0	5321	0	2	233	2	3	80807	80583	80100	80853	81212	81170	81170	80846
80204	80850	709	0	1	0	0	0	12	0	0	3848	521	80725	80687	80732	403461	0	49	78127	0	81086	80986	70415	107	70642	80728	81001	80975	81120	164	24	1	80201	100	99	80100	0	0	0	1	0	3	0	0	5110	28	0	16	0	0	80037	80105	80100	80042	80041	80041	80042	80041
80204	80040	702	0	0	0	0	0	12	0	0	77	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	3	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	12	0	0	35	25	80221	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	3	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	12	0	0	764	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80234	80234	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	5110	0	2	25	2	2	80057	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	643	1	1	0	21	0	1	83	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	1	3	0	5022	0	6	25	7	4	80024	80010	0	5	80010	80036	80036	80036	80036	80036
80024	80035	645	1	1	0	12	0	1	41	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	45	0	5022	0	4	25	4	7	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	644	1	1	0	0	0	1	83	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5022	0	7	25	7	7	80024	80010	0	0	80010	80036	80073	80036	80036	80036
80024	80035	646	1	1	0	537	0	1	1158	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5022	0	4	25	4	7	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	1	1	0	0	0	1	58	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	2	1	80021	10	9	80010	0	0	0	0	3	0	5022	0	7	25	7	4	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	1	1	0	0	0	1	106	25	80020	80020	80020	400100	0	98	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	2	1	80021	10	9	80010	0	0	0	0	0	0	5022	0	7	25	7	4	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	1	1	0	0	0	1	41	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	3	0	5022	0	7	25	7	4	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	700	1	1	0	12	0	1	136	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5022	2	4	25	7	7	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	702	1	1	0	0	0	1	111	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	2043	0	5022	0	6	25	6	3	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	745	1	1	0	0	0	1	43	25	80020	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5022	0	3	25	3	6	80024	80010	0	0	80010	80036	80036	80036	80036	80036

AUTIZA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations