Firestorm: SDIV (fast, 32-bit) measurements

Code:

  sdiv w0, w1, w2

Initialization

  mov w1, #0
  mov w2, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
1004	2038	15	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	39	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	0	350	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	16	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	9	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039
1004	2038	15	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	73	1	16	1	1	1981	1000	0	1000	2039	2039	2039	2039	2039

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv w0, w1, w2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	674	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	61152	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	3	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	12	176	0	390	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90216	176	1	1	30201	100	99	100	30100	100	0	1	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	0	103	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	4	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	15	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90081
30204	90035	674	0	0	0	0	9	0	0	61	81120	109	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	8	0	0	0	0	1910	4	16	2	2	89751	30000	30100	90212	90036	90036	90036	90036
30204	90035	676	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	2	16	2	3	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	4	0	24	352	0	103	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	0	726	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30617	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	2	1	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90215
30204	90035	688	0	0	0	4	0	0	0	61	81120	25	30155	30100	30100	8522656	1	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	2	16	2	3	89751	30000	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90035	675	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	3	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	61	81210	42	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	3	16	3	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	61	81210	25	30010	30010	30116	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	3	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	4	16	3	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	1	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	726	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	3	1890	3	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	3	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30126	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	2	16	4	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	2	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	9	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1890	4	16	1	2	89751	30000	30010	90036	90036	90036	90036	90036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv w0, w1, w2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	674	0	0	1	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	7	0	0	1910	2	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	3	0	1910	1	17	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	156	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	61	81120	42	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	1	0	0	24	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	189	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	0	1	89751	30000	30100	90036	90036	90068	90036	90036
30204	90035	674	0	0	0	0	0	0	726	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	1	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	1	3	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	183	0	1910	1	16	1	0	89751	30000	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90035	674	0	0	0	0	0	0	0	436	81210	25	30010	30010	30010	8522901	0	0	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	7	16	6	6	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	0	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1915	6	16	5	5	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	0	0	0	726	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	6	16	6	6	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	6	16	6	5	89751	30000	30010	90036	90036	90036	90036	90036
30024	90074	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90076	176	1	1	30021	10	9	10	30010	10	37	0	0	0	1890	7	16	7	7	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	0	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	7	16	7	7	89751	30000	30010	90036	90036	90036	90125	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	0	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	7	16	7	7	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	1	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	6	16	7	5	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	0	0	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	1	0	1890	7	16	7	9	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	0	0	0	0	0	726	81210	25	30010	30010	30010	8522901	0	0	49	86955	90035	90035	85922	0	3	86265	30010	30020	60020	90035	176	2	1	30021	10	9	10	30010	10	0	9	0	0	1890	7	16	7	7	89751	30000	30010	90036	90036	90036	90036	90036

Test 4: throughput

Count: 8

Code:

  sdiv w0, w8, w9
  sdiv w1, w8, w9
  sdiv w2, w8, w9
  sdiv w3, w8, w9
  sdiv w4, w8, w9
  sdiv w5, w8, w9
  sdiv w6, w8, w9
  sdiv w7, w8, w9

Initialization

  mov w8, #0
  mov w9, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160038	1198	0	0	0	61	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	61	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	2	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1198	1	0	0	103	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	2	3	0	6	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	726	79950	25	80100	80100	80261	4399798	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	0	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	61	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	726	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160328	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	2	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	61	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	726	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	1	0	0	61	79950	25	80100	80100	80100	4399225	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	171	176	61	79950	25	80100	80100	80100	4399225	49	153927	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	160038	1199	0	0	0	4	3	15	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	2	0	0	33	0	0	0	5020	0	3	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160078	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	1	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	2	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	3	160038	160038	149923	3	150018	80010	80020	160140	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5034	0	1	16	2	2	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80024	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	1	16	1	1	159980	80000	0	80010	160081	160039	160039	160039	160039
80025	160038	1198	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	1	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	1	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160080	1198	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	1	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	420	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	1	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	2	0	0	0	0	0	5020	0	1	16	1	1	159980	80000	0	80010	160039	160039	160039	160039	160281

SDIV (fast, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations