Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SDIV (medium, 64-bit)

Test 1: uops

Code:

  sdiv x0, x1, x2
  mov x1, #0xffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420391506195025100010001000537250203920391801318971000100020002039261111001100000731161119801000100020402040204020402040
100420391506195025100010001000537250203920391801318971000100020002039261111001100000731161119801000100020402040204020402040
100420391506195025100010001000537250203920391801318971000100020002039261111001100000731161119801000100020402040204020402040
100420391606195025100010001000537250203920391801318971000100020002039261111001100003731161119801000100020402040204020402040
100420391506195025100010001000537250203920391801318971000100020002039261111001100000731161119801000100020402040204020402040
100420391506195025100010001000537250203920391801318971000100020002039261111001100000731161119801000100020402040204020402040
100420391506195025100010001000537251203920391801318971000100020002039261111001100030731161119801000100020402040204020402040
100420391506195025100010001000537250203920391801318971000100020002039261111001100000731161119801000100020402040204020402040
100420391506195025100010001000537251203920391801318971000100020002039261111001100003731161119801000100020402040204020402040
100420391506195025100010001000537251203920391801318971000100020002039261111001100000731161119801000100020402040204020402040

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0
  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
3020410003574900017606642912612530100301003010094934431499695501000351000359587339624230100302006020010003519311302011009910030100100000001910021711997223000030100100036100036100036100036100036
302041000357490000061912612530100301003010094934431499695501000351000359587339624230100302006020010006419311302011009910030100100000001910011711997223000030100100036100036100036100036100036
302041000357490000061912612530100301003010094934431499695501000351000359587339624230100302006020010003537811302011009910030100100000001910011911997223000030100100036100036100036100036100036
302041000357490000061912612530100301003022294934431499695501000351000359587339624230100302006020010003519311302011009910030100100000001910011711997223000030100100036100036100036100036100036
3020410003574900000726912612530100301003010094934431499406101000351000359587339624230100302006020010003519311302011009910030100100000001910011711997223000030100100036100036100036100036100036
302041000357490100061912612530100301003010094934431499695501000351000359587339624230100302006020010003519311302011009910030100100009001910011711997223000030100100036100036100036100036100036
3020410003574900000726912612530100301003010094934431499695501000351000359587339624230100302006020010003519311302011009910030100100000001910011711997223000030100100036100036100036100036100036
302041000357490000061912612530100301293010094934431499695501000351000359587339624230100302006020010003519311302011009910030100100000001910011711997223000030100100036100036100036100036100036
302041000357500000061912612530100301003010094934431499695501000351000359587339624230100302006020010003519311302011009910030100100000001910011711997223000030100100036100036100036100036100036
302041000357490000061912612530100301003010094934431499695501000351000359587339624230100302006020010003519311302011009910030100100000001910011711997223000030100100036100036100036100036100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
30024100035749000061911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100003000189031622997143000030010100036100036100036100036100036
30024100035749000061911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100000000191421622997143000030010100036100036100036100036100036
30024100035749000061911822530010300103001094787671499695501000351000359588539626530010300206024410003519311300211091030010100000000189021620997143000030010100036100036100036100065100036
30024100035749000061911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100000000189021622997143000030010100036100036100036100036100036
30024100035749000061911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100000000189021622997143000030010100036100036100036100036100036
30024100035749000184797914442530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100000000189021623997143000030010100036100036100036100036100036
30024100076750000061911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100006200190821622997143000030010100036100036100036100036100036
300241000817500101261911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100000000189022322997573000030010100081100169100036100079100128
300241000357490001261911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100000001189022422997143000030010100036100036100036100036100036
30024100035749000061911822530010300103001094787671499695501000351000359588539626530010300206002010003519311300211091030010100000000189021622997143000030010100066100036100036100036100036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0
  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0f18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)d8ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
3020410003575010010006191261253010030100302189493443104996955100035100035958733962423010030200602001001261931130201100991003010010000006001910317022997223000030100100036100036100036100077100081
30204100035749000000061912612530100301003010094934431049969981000351000359587339624230100302006020010003519311302011009910030100100020199001910217022997223000030100100036100036100036100036100036
302041000357510000013204292912614630100301003010094866081049970001000811000809586179626230207303226042410008019321302011009910030100100420010520192821721422997223003630100100079100036100036100036100082
302041000357500003214401255912616630135301343031794967010049969551000351000359587310962423010030200602001000351931130201100991003010010000004550001965226022997223000030100100127100126100125100124100125
302041000357491000000829126167301313013130297949741710499704210003510003595873396242301003032160440100124193213020110099100301001000021105001929259022997223014030100100036100036100036100036100081
3020410003575000000153061912612530100301003010094934431049969551000351000809587339626530203304326065410012519331302011009910030100100040087001929233023997923000030100100036100080100036100036100036
3020410003574900000120726912612530100301003010094934430049969551000351000359587339624230100302006020010003519311302011009910030100100000012001910217022997223000030100100036100036100036100036100036
3020410003575000000006191261253010030100301009493443004996955100035100035958733962423010030200602001000351931130201100991003010010000009001910217022997223000030100100036100036100036100036100036
3020410003574900000006191261253010030100301009493443004996955100035100035958733962423010030200602001000351931130201100991003010010000009001910217022997223000030100100036100036100036100036100036
30204100035750000000025191261253010030100301009493443004996955100035100035958733962423010030200602001000351931130201100991003010010000009001910217022997223000030100100036100036100036100036100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
30024100035749000006191182253001030010300109478767149969551000351000359588539626530010300206002010003519311300211091030010100600189071622997143000030010100036100036100036100036100036
30024100035749000006191301253001030010300109478767149969551000351000359588539626530010300206002010003519311300211091030010100900189021622997143000030010100036100036100036100036100036
300241000357500000061911821133003930035304149500323049971321002121002119589039626530010300206002010003519311300211091030010104000189021622997143000030010100036100036100036100036100036
30024100035749103006191182253001030010300109478767149969551000351000359588539626530010300206002010003519311300211091030010103000189021622997143000030010100036100036100036100036100036
30024100035749010006191182253001030010300109478767049969551000351000359588539626530010300206002010003519311300211091030010100001189021623997143000030010100036100036100036100036100036
30024100035749000006191182253001030010300109478767049969551000351000359588539626530010300206002010003519311300211091030010100000189021622997143000030010100036100068100036100036100036
30024100035749000006191182253001030010300109478767149969551000351000359588539626530010300206002010003519311300211091030010100000189021622997143000030010100036100036100036100036100036
30024100035750000006191182253001030010300109478767149969551000351000359588539626530010300206002010003519311300211091030010100000189021622997143000030010100036100036100036100036100036
30024100035749000006191182253001030010300109478767049969551000761000359588539626530010300206002010003519311300211091030010100000189021622997143000030010100036100036100036100036100036
3002410003575000016806191182253001030010300109478767149969551000351000359588539626530010300206002010003519311300211091030010100000189021622997143000030010100036100077100036100036100036

Test 4: throughput

Count: 8

Code:

  sdiv x0, x8, x9
  sdiv x1, x8, x9
  sdiv x2, x8, x9
  sdiv x3, x8, x9
  sdiv x4, x8, x9
  sdiv x5, x8, x9
  sdiv x6, x8, x9
  sdiv x7, x8, x9
  mov x8, #0xffffffff
  mov x9, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802051600391199000000617995025801008010080100439922504915695901600391600391499013149997801008020016020016003926111802011009910080100100000005110216111599808000080100160040160040160040160040160040
8020416003911980000001267995025801008010080100439922514915695931600391600391499013149997801008020016020016003926111802011009910080100100000005110116111599808000080100160040160040160040160040160040
8020416003911980000004417995025801008010080100439922504915695901600391600391499013149997801008020016020016003927511802011009910080100100000005110116111599808000080100160040160040160040160040160040
802041600391198000000617995025801008010080100439922504915695901600391600391499013149997801008020016020016003926111802011009910080100100000005110116131600428000080100160040160040160040160040160040
802041600391199000000617995025801008010080100439922504915695901600391600391499013149997801008020016020016003926111802011009910080100100000005110116521599808000080100160040160040160040160040160040
802041600391198000000617995025801008010080100439922504915695901600391600391499013149997801008020016020016007826111802011009910080100100000005110116111599808000080100160040160040160040160040160040
8020416003911980000005487995025801008010080100439922509815695901600391600391499013149997801008020016020016003926111802011009910080100100000005110116111599808000080100160040160040160040160040160040
8020516003911980000001037995025801258012580163439963304915695901600391600391499013149997801498020016029816033526141802011009910080100100130005112116111599808000080100160040160040160040160040160040
80204160139119910233028001037995025801008010080100439922504915695901600391600391499013149997801008020016020016003926111802011009910080100100030005110116121599808002580100160040160040160040160040160040
802041600391199000000947995025801008010080125439922509815695901600391600391499013149997801008020016020016003926111802011009910080100100000005110116221599808000080100160040160083160040160040160075

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
8002416003911980000072679950258001080010800104398775149156959160039160039149923315001980010800201600201600392611180021109108001010000270050201161115998080000080010160040160040160040160040160040
80024160039119900090617995025800108001080010439877514915695916003916003914992331500198001080020160020160039261118002110910800101000000050201161115998080000080010160040160040160040160040160040
800241600391198000007267995025800108001080010439877514915695916003916003914992331500198004880020160020160039261118002110910800101000000050521161115998080000080010160040160040160040160040160040
80024160039119900000617995025800108001080010439877514915695916003916003914992331500198001080020160020160039261118002110910800101000000050201161115998080000080010160040160040160040160040160040
800241600391199000004937995025800108001080010439877514915695916003916003914992331500198001080020160020160039261118002110910800101000000050201161115998080000080010160040160081160040160040160040
8002416003911990000014977995025800108001080010439877514915695916003916003914992331500198001080020160020160039261118002110910800101000400150201161115998080000080010160040160040160040160040160040
80024160039119900000617995025800108001080010439877514915695916003916003914995331500198001080020160020160039261118002110910800101000000050201161115998080000080010160040160040160040160040160040
80024160039119800000617993825800108001080010439877514915695916003916003914992331500198001080020160020160039261118002110910800101000000050201161115998080000080010160040160040160040160040160040
800241600391198000007267995025800108001080010439877514915695916003916003914992331500198001080020160020160039261118002110910800101000000050201161115998080000080010160040160040160040160040160040
80024160039119800000617995025800108001080010439877514915695916003916003914992331500198001080020160020160039261118002110910800101000000050201161115998080000080010160040160040160040160040160040