Firestorm: SDIV (medium, 64-bit) measurements

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2039	15	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	16	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	3	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	3	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	3	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	749	0	0	0	176	0	6642	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	2	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100064	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	378	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	19	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30222	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	726	91261	25	30100	30100	30100	9493443	1	49	94061	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	1	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	9	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	726	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30129	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	0	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	3	0	0	0	1890	3	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1914	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60244	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	0	99714	30000	30010	100036	100036	100036	100065	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	18	4797	91444	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100076	750	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	6	2	0	0	1908	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100081	750	0	1	0	12	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	23	2	2	99757	30000	30010	100081	100169	100036	100079	100128
30024	100035	749	0	0	0	12	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	1	1890	2	24	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100066	100036	100036	100036	100036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d8	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	750	1	0	0	1	0	0	0	61	91261	25	30100	30100	30218	9493443	1	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100126	193	1	1	30201	100	99	100	30100	100	0	0	0	0	6	0	0	1910	3	17	0	2	2	99722	30000	30100	100036	100036	100036	100077	100081
30204	100035	749	0	0	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	0	49	96998	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	2	0	1	99	0	0	1910	2	17	0	2	2	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	751	0	0	0	0	0	132	0	4292	91261	46	30100	30100	30100	9486608	1	0	49	97000	100081	100080	95861	7	96262	30207	30322	60424	100080	193	2	1	30201	100	99	100	30100	100	4	2	0	0	105	2	0	1928	2	17	214	2	2	99722	30036	30100	100079	100036	100036	100036	100082
30204	100035	750	0	0	0	3	2	144	0	1255	91261	66	30135	30134	30317	9496701	0	0	49	96955	100035	100035	95873	10	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	4550	0	0	1965	2	26	0	2	2	99722	30000	30100	100127	100126	100125	100124	100125
30204	100035	749	1	0	0	0	0	0	0	82	91261	67	30131	30131	30297	9497417	1	0	49	97042	100035	100035	95873	3	96242	30100	30321	60440	100124	193	2	1	30201	100	99	100	30100	100	0	0	2	1	105	0	0	1929	2	59	0	2	2	99722	30140	30100	100036	100036	100036	100036	100081
30204	100035	750	0	0	0	0	0	153	0	61	91261	25	30100	30100	30100	9493443	1	0	49	96955	100035	100080	95873	3	96265	30203	30432	60654	100125	193	3	1	30201	100	99	100	30100	100	0	4	0	0	87	0	0	1929	2	33	0	2	3	99792	30000	30100	100036	100080	100036	100036	100036
30204	100035	749	0	0	0	0	0	12	0	726	91261	25	30100	30100	30100	9493443	0	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	12	0	0	1910	2	17	0	2	2	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	0	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	9	0	0	1910	2	17	0	2	2	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	0	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	9	0	0	1910	2	17	0	2	2	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	0	0	0	0	251	91261	25	30100	30100	30100	9493443	0	0	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	9	0	0	1910	2	17	0	2	2	99722	30000	30100	100036	100036	100036	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	6	0	0	1890	7	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91301	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	9	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	0	0	61	91182	113	30039	30035	30414	9500323	0	49	97132	100212	100211	95890	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	4	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	0	3	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	3	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	1	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	1	1890	2	16	2	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100068	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	100076	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	168	0	61	91182	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100077	100036	100036	100036

Test 4: throughput

Count: 8

Code:

  sdiv x0, x8, x9
  sdiv x1, x8, x9
  sdiv x2, x8, x9
  sdiv x3, x8, x9
  sdiv x4, x8, x9
  sdiv x5, x8, x9
  sdiv x6, x8, x9
  sdiv x7, x8, x9

Initialization

  mov x8, #0xffffffff
  mov x9, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80205	160039	1199	0	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	0	0	126	79950	25	80100	80100	80100	4399225	1	49	156959	3	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	0	0	441	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	275	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	3	160042	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	5	2	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160078	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	0	0	548	79950	25	80100	80100	80100	4399225	0	98	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80205	160039	1198	0	0	0	0	0	0	103	79950	25	80125	80125	80163	4399633	0	49	156959	0	160039	160039	149901	3	149997	80149	80200	160298	160335	261	4	1	80201	100	99	100	80100	100	1	3	0	0	0	5112	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160139	1199	1	0	2	330	280	0	103	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	3	0	0	0	5110	1	16	1	2	159980	80025	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	0	0	94	79950	25	80100	80100	80125	4399225	0	98	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	2	2	159980	80000	80100	160040	160083	160040	160040	160075

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	160039	1198	0	0	0	0	0	726	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	27	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	9	0	61	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	0	0	0	0	726	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80048	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5052	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	0	493	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160081	160040	160040	160040
80024	160039	1199	0	0	0	0	0	1497	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	4	0	0	1	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149953	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	0	0	0	0	61	79938	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	0	0	0	0	726	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	1	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	1	16	1	1	159980	80000	0	80010	160040	160040	160040	160040	160040

SDIV (medium, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations