Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (ISHLD)

Test 1: uops

Code:

  dsb ishld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
100417037127017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417037128017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417037127017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417037127017017158011000100010006000149139521485917032316890100010001703217032111001100010001073116111687310001703317033170331703317033
100417037127017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417037128017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417037128017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417037128017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170371281217017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417037128017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033

Test 2: throughput

Code:

  dsb ishld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 17.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1020417003712730000018011700171597001010010010000100100005005980004916695215098617003231687401010020010000200170032135919111020110099100100100001000001000060300071021622169952010000100170033170033170033170033170033
102041700371274000000001700171597001010010010000100100005005980004916695215093517005831687401010020010000200170050135919111020110099100100100001000001000000000071021622169838010000100170033170033170033170033170033
102041700371274000000001700331597001010010010000100100005005980004916695215093517003231687401010020010000200170032135919111020110099100100100001000001000000000071021622169838010000100170033170033170033170033170033
10204170037127300000000170017159700101001001000010010000500598000491669521509351700323168740101002001000020017003213591911102011009910010010000100000100000022800071021622169838010000100170142170033170033170033170033
102041700371274000000001700171597001010010010000100100005005980004916695215103517003231687401010020010000200170032135919111020110099100100100001000001000000020071021622169838010000100170033170033170033170033170033
10204170037127400000000170017159700101001001000010010000500598000491669521509351700323168740101002001000020017003213591911102011009910010010000100000100000039000071021622169838010000100170033170033170033170033170033
102041700371273000000001700171597001010010010000100100005005980004916695215093517003231687401010020010000200170032135919111020110099100100100001000001000000000071021622169838010000100170033170033170033170033170033
102041700371274000000001700171597001010010010000100100005005980004916695215098017003231687401010020010000200170032135919111020110099100100100001000001000000000071021622169838010000100170033170033170033170033170033
102041700371273000000001700171597001010010010000100100005005980004916695215093517003231687401010020010000200170032135919111020110099100100100001000001000000000071021622169838010000100170033170033170033170033170033
10204170037127300000000170017159700101001001000010010015500598000491669521509511700323168740101002001000020017003213591911102011009910010010000100000100000022800071021622169838010000100170033170033170033170033170033

1000 unrolls and 10 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1002417003212740017001715978610010101000010100005059980149166952150029170032316876210010201000020170032170032111002110910101000010010000000640216331698381000010170033170033170033170033170033
1002417003212730017001715978610010101000010100005059980149166952149957170032316876210010201000020170032170032111002110910101000010010000000640216321698381000010170033170033170033170033170033
1002417003212730017001715978610010101000010100005059980149166952149957170032316876210010201000020170032170032111002110910101000010010000000640216221698381000010170033170033170033170033170033
1002417003212740017001715978610010101000010100005059980149166952150031170032316876210010201000020170032170032111002110910101000010010000000640216331698381000010170033170033170033170033170033
1002417003212740017001715978610020101000010100005059980149166952149957170032316876210010201000020170032170032111002110910101000010010000000640216331698381000010170033170033170033170033170033
1002417003212730017001715978610010101000010100005059980198166952149957170032316876210010201000020170032170032111002110910101000010010000300640316331698381000010170033170033170033170033170033
1002417003212740017001715978610010101000010100005059980149166952150089170032316876210010201000020170032170032111002110910101000010010000000640216331698381000010170033170033170033170033170033
1002417003212930017001715978610010101000010100005059980149166952149957170032316876210010201000020170032170032111002110910101000010010000000640216231698381000010170033170033170033170033170033
1002417003212730017001715978610010101000010100005059980149166952149957170032316876210010201000020170032170032111002110910101000010010000000640316221698381000010170033170033170033170033170033
1002417003212730017001715978610010101000010100005059980149166952150019170032316876210010201000020170032170032111002110910101000010010000000640316331698381000010170033170033170033170033170033