Firestorm: AUTIB measurements

Code:

  autib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	66	66	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	2	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	6	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	1	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	6	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	396	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	4	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	9	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	6	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7110	7030
1004	7029	65	0	82	5824	25	1000	1000	1000	178330	0	49	3988	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	6	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e8	? int output thing (e9)	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	617	0	0	0	0	18	0	0	441	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20232	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	655	0	0	0	0	0	0	0	726	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68775	10284	10290	20200	70029	912	1	1	10201	100	99	10100	0	0	0	3	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	655	0	0	0	0	18	0	0	103	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	3	0	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	655	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	3	1	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	618	0	0	0	0	0	0	0	61	59824	25	10200	10204	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	1	3	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	1871	1	1	10201	100	99	10100	0	0	0	0	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	726	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	656	0	0	0	0	0	0	0	726	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	2	0	0	710	1	79	1	1	69872	0	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	619	0	0	0	0	12	0	0	61	59824	25	10200	10204	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	1	1400	0	710	1	79	1	1	69796	0	10100	0	0	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	683	0	0	0	0	0	3251	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	1	640	4	79	4	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	658	0	0	0	0	0	439	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	4	79	4	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	198	59815	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	4	79	4	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	208	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	3	0	640	4	79	4	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	618	0	0	0	0	0	535	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	4	79	4	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	584	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	4	79	4	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	461	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	3	0	649	4	79	4	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	639	0	0	12	0	0	368	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	4	79	4	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	276	59824	25	10020	10020	10048	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	1	3	0	640	3	79	3	4	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	131	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	3	87	3	4	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  autib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	bb	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	699	0	0	0	0	0	0	82	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	2	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	697	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	0	61	69795	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	1	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	702	0	0	0	12	0	0	103	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20263	20200	40200	80029	144	2	1	30201	100	99	30100	1	12	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	746	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	702	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80055	80030	80030	80030	80030
30204	80029	717	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	744	0	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	701	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	49	76988	80029	80029	75961	3	76181	20200	20282	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	702	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	18	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80154	80030	80030	80918

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5e	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
30024	80113	696	0	0	0	0	0	0	0	88	1	61	69799	25	20025	20025	20020	4952048	0	0	49	76949	80029	80029	75969	3	76203	20020	20102	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	0	2	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	700	0	0	0	0	0	0	0	0	0	727	69799	25	20020	20029	20020	4952048	0	1	49	76995	80029	80029	75983	3	76203	20087	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	2	2	79803	20010	0	30010	80030	80030	80030	80030	80070
30024	80029	717	0	0	0	1	0	0	0	0	0	61	69799	46	20025	20020	20020	4951303	0	1	49	76949	80029	80029	75983	7	76209	20086	20020	40020	80029	305	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	18	4	2	79803	20014	0	30010	80069	80030	80030	80030	80030
30024	80029	750	0	0	0	0	0	0	0	176	0	61	69799	25	20020	20020	20086	4952048	0	1	49	76949	80069	80029	75969	3	76203	20085	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	2	0	0	0	0	0	1909	2	72	2	2	79803	20010	0	30010	80030	80075	80075	80030	80030
30024	80029	700	0	0	0	0	0	0	132	0	0	1622	69799	25	20020	20020	20084	4952048	0	0	49	76949	80029	80029	75983	3	76203	20087	20100	40020	80029	144	1	1	30021	10	9	30010	0	0	0	1	0	1825	0	0	1909	2	72	2	2	79803	20010	0	30010	80030	80069	80075	80152	80030
30024	80029	700	0	0	1	0	0	0	828	660	0	61	69799	25	20020	20020	20088	4952048	0	0	49	76949	80029	80029	75983	8	76203	20020	20020	40020	80075	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	2	3	79803	20010	0	30010	80075	80075	80030	80030	80030
30024	80029	700	0	0	0	1	0	0	0	0	0	251	69799	25	20020	20020	20087	4952048	0	0	49	76994	80069	80075	75983	7	76218	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	96	2	2	79803	20010	0	30010	80075	80030	80030	80030	80075
30024	80029	700	0	0	0	0	0	0	132	0	0	117	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80069	75983	3	76203	20020	20182	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	2	2	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80060	750	0	0	0	0	0	1	0	0	0	61	69799	25	20020	20024	20020	4952048	0	0	49	76949	80029	80029	75983	3	76218	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	3	2	1	1890	2	72	2	2	79803	20014	0	30010	80030	80030	80030	80030	80030
30024	80029	700	0	1	0	0	1	1	0	0	0	591	69799	25	20020	20020	20020	4950575	0	1	49	76949	80029	80029	75975	3	76203	20097	20020	40182	80029	144	1	1	30021	10	9	30010	3	0	0	1	0	1915	2	0	1890	2	72	2	2	79803	20010	0	30010	80030	80030	80030	80206	80030

Test 4: throughput

Count: 8

Code:

  autib x0, x8
  autib x1, x8
  autib x2, x8
  autib x3, x8
  autib x4, x8
  autib x5, x8
  autib x6, x8
  autib x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80062	697	0	0	0	0	0	0	0	510	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	3	0	0	3	0	0	5110	2	25	3	2	80838	80604	80100	81125	81073	80895	81037	81164
80204	81125	707	0	0	0	20	24	3048	1612	9579	45	80200	80200	80200	401000	1	49	77681	80897	80760	70325	86	70741	80620	80767	161892	80984	164	18	1	80201	100	99	80100	2	2	0	1	2	11563	2	0	5524	2	33	2	2	80296	80542	80100	80080	80042	80041	80042	80036
80204	80035	787	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	3	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	750	0	0	0	0	0	132	0	77	25	80200	80200	80200	401000	0	49	76955	80080	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	3	0	0	5110	2	25	2	2	80058	80100	80100	80036	80036	80036	80036	80036
80204	80035	696	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5124	2	25	2	2	80025	80100	80100	80082	80036	80036	80036	80036
80204	80035	794	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	2	1	80201	100	99	80100	0	0	0	0	0	0	0	1	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80082	80036
80204	80035	699	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80081	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	15	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	749	0	0	0	0	0	0	0	35	25	80200	80200	80200	401107	0	49	76955	80035	80035	69966	3	69984	80200	80200	160268	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	700	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80060	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	699	0	0	0	0	0	0	700	25	80020	80020	80020	400100	1	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	7	25	3	4	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	696	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	5	25	4	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	12	0	750	25	80040	80020	80020	400100	0	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	3	0	0	5073	0	0	4	25	4	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	700	25	80020	80020	80020	400100	0	0	49	76955	80035	80035	69988	11	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	3	0	0	5020	0	0	4	25	3	5	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	4	25	4	4	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	120	25	80020	80020	80020	400100	0	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	5	25	5	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	48	0	0	5020	0	0	5	25	4	4	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	2	25	3	4	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	0	49	76955	80035	80099	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	2	25	5	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	225	25	80020	80020	80020	400100	1	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	0	4	25	5	3	80024	80010	0	80010	80036	80036	80036	80036	80036

AUTIB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations