Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SBFX (64-bit)

Test 1: uops

Code:

  sbfx x0, x0, #3, #7
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100410358061862251000100010001691610351035728386810001000100010354111100110001073241229371000100010361036103610361036
100410357061862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
100410358961862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
100410358061862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
100410357061862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
100410358061862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
100410358061862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
1004103581261862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
100410357961862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036
100410358661862251000100010001691610351035728386810001000100010354111100110000073241229371000100010361036103610361036

Test 2: Latency 1->2

Code:

  sbfx x0, x0, #3, #7
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
10204100357500829877251010010100101008866414969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100010071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664049695510035100358580387221010010200102001003541111020110099100101001000430071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
10024100357584619863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575210619863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010101064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878404969551008110035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575216619863251001010010100108878404969551003510035860238740100101002010020100784111100211091010010100064024122994010000100101003610036100361003610036
1002410035750829863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036

Test 3: throughput

Count: 8

Code:

  sbfx x0, x8, #3, #7
  sbfx x1, x8, #3, #7
  sbfx x2, x8, #3, #7
  sbfx x3, x8, #3, #7
  sbfx x4, x8, #3, #7
  sbfx x5, x8, #3, #7
  sbfx x6, x8, #3, #7
  sbfx x7, x8, #3, #7
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413390100110282780136801368014840071014910310313390133903326633368014880264802641339039118020110099100801001000001115119116211338780036801001339113391133911339113391
8020413390101110282780136801368014840071014910310013390133903326633368014880264802641339039118020110099100801001000001115119116111338780036801001339113391133911339113391
8020413390100110282780136803988014840071014910310013390133903326633368014880264802641339039118020110099100801001002001115120216121338780036801001339113391133911339113391
8020413390100110282780136801368014840071014910310013390133903326633368014880264802641339039118020110099100801001000001115119216111338780036801001339113391133911339113391
8020413390101110282780136801368014840071004910310013390133903326633368014880264802641339039118020110099100801001000031115119116111338780036801001339113391133911339113391
8020413390100110702780136801368014840071014910310013390133903326633368014880264802641339039118020110099100801001000201115119116111338780036801001339113391133911339113391
8020413390101110282780136801368014840071014910310013390133903326633368014880264802641339039118020110099100801001000001115119116111338780036801001339113391133911339113391
8020413390100110282780136801368014840071014910310013390133903326633368014880264802641339039118020110099100801001000001115120216111338780036801001339113391133911339113391
8020413390100110282780136801368014840071014910310013390133903326633368014880264802641339039118020110099100801001000001115120216121338780036801001339113391133911339113391
8020413390100110282780136801368014840071014910310013390133903326633368014880264802641339039118020110099100801001000001115119216221338780036801001339113391133911339113391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
8002413387100069402580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010002502061911133688000000800101337213372133721337213372
800241337110000352580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
800241337110000352580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
80024133711000303352580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
80024133711000213352580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
8002413371100001062580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
800241337110000352580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
800241337110000562580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
800241337110000632580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372
800241337110000582580010800108001040005004910291133711337133303334880010800208002013371391180021109108001010000502011911133688000000800101337213372133721337213372