Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AND (register, asr, 32-bit)

Test 1: uops

Code:

  and w0, w0, w1, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000732671117812000100020362036203620362036
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351509611000173525200020001000325700203520351575318421000100020002035421110011000380731671117812000100020362036203620362036
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035160061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  and w0, w0, w1, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351500061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150023161100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150020761100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200781500061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003515001561100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515000043206110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640463331979220000100102003620036200362003620036
10024200351500000032110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
1002420035150000006110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
1002420035150000006110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
10025200351500002106110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
1002420035150000006110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
1002420035150000006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
1002420035150000006110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
1002420035150100006110000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036
10024200351490000010310000197432520010200101001018531004916955200352003518451318718100101002020020200354211100211091010010100640363331979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  and w0, w1, w0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
1020420035150002771000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710259221979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000003006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049139172003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515000000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620079200362003620036

Test 4: throughput

Count: 8

Code:

  and w0, w8, w9, asr #17
  and w1, w8, w9, asr #17
  and w2, w8, w9, asr #17
  and w3, w8, w9, asr #17
  and w4, w8, w9, asr #17
  and w5, w8, w9, asr #17
  and w6, w8, w9, asr #17
  and w7, w8, w9, asr #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802042677220000000006180000260942516010016010080100164318492364502672526725166153166778010080200160200267253911802011009910080100100000000105051102221126717160000801002672626726267262672626726
8020426725200000000061800002609425160100160100801001643184923645026725267251661531667780100802001602002672539118020110099100801001000000109051101221126717160000801002672626726267262672626726
802042672520000000006180000260942516010016010080100164318492364502672526725166153166778010080200160200267253911802011009910080100100000000114051101221126717160000801002672626726267262672626726
802042672520000000006180000260942516010016010080100164318492364502672526725166153166778010080200160200267253911802011009910080100100000010114051101221126717160000801002672626726267262672626726
80204267252000000000618000026094251601001601008010016431849236450267252672516615316677801008020016020026725391180201100991008010010000000060051101221226717160000801002672626788267262672626785
802042672520700000005368000026094251601001601008010016431849236450267252672516615101667780100802001606342672539118020110099100801001000000010051101221126717160000801002672626726267262672626726
8020426725200000001560450800002609425160291160293807411705404923645026777268461661531667780100804181610682678639318020110099100801001004000000051101221126717160000801002672626726267262672626726
80204267252000000000103800002609425160100160100801001643184923645026725267251661531667780100802001602002672539118020110099100801001000000100051101221126717160000801002672626726267262672626726
802042672520000000120189180000260942516010016010080100164318492364502672526725166153166778010080200160200267253911802011009910080100100000000204051101221126764160000801002672626726267262672626726
8020426725200000009082800002609425160100160100801001643184923645026725267251661531667780100802001602002672539118020110099100801001000000003051101221126717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)033f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426735200618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010755020142216626704160000800102671226712267122671226712
800242671120061800002128025160010160010802821631420492363126711267111662331668580010800201600202671139118002110910800101066502062261326704160000800102671226712267122671226712
80024267112006180000212802516001016001080010163142049236312671126711166233166858001080020160020267113911800211091080010109050201622161626704160000800102671226712267122671226712
800242671120061800002128025160010160010800101631421492363126711267111662331668580010800201600202671139118002110910800101035020132261626704160000800102671226712267122671226712
800242671120761800002128025160010160010800101631421492363126711267111662331668580363800201600202671139118002110910800101045502062216626704160000800102671226712267122671226712
8002426711200618000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010875020162216626704160000800102671226712267122671226712
800242671120061800002128025160010160010800101631421492363126711267111662331668580010800201600202671139118002110910800101090502062261626704160000800102671226712267122671226712
800242671120061800002128025160010160010800101631421492363126711267111662331668580010800201600202671139118002110910800101095020162216626704160000800102671226712267122671226712
80024267112006180000212802516001016001080010163142049236312671126711166233166858001080020160020267113911800211091080010100502062261626704160000800102671226712267122671226712
8002426711200618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010935020162261626704160000800102671226712267122671226712