Firestorm: MOV (from sp, 64-bit) measurements

Code:

  mov x0, sp

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	60	6d	6e	map rewind (75)	map stall (76)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	1	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	48	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153
1004	152	1	27	150	0	152	152	3	10	1000	1000	152	35	1	1	1001	1000	0	74	1	15	1	1	149	1000	153	153	153	153	153

Count: 8

Code:

  mov x0, sp
  mov x1, sp
  mov x2, sp
  mov x3, sp
  mov x4, sp
  mov x5, sp
  mov x6, sp
  mov x7, sp

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1258

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	10064	78	0	1	0	0	0	0	63	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061
80204	10060	81	0	0	0	0	0	0	63	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	1	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061
80204	10060	77	0	0	0	0	0	0	35	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	1	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	35	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	35	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	35	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061
80204	10060	78	0	0	0	0	0	0	35	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061
80204	10060	77	0	0	0	0	0	0	35	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	5112	2	16	2	2	10057	80100	10061	10061	10061	10125	10061
80204	10060	78	0	0	0	0	0	0	130	9554	100	100	100	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	1	1	80201	100	99	100	80100	100	0	0	0	5112	2	48	2	2	10084	80100	10125	10061	10061	10061	10100
80204	10133	78	0	0	0	1	1	0	35	9554	100	100	101	500	0	49	6980	10060	10060	0	3	18	100	80200	80200	10060	35	2	1	80201	100	99	100	80100	100	0	2	180	5112	2	16	2	2	10057	80100	10061	10061	10061	10061	10061

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1255

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	10043	78	0	12	0	237	9982	10	10	10	50	0	1	0	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5030	5	1	13	16	8	10	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	78	1	0	0	326	9982	10	10	10	50	0	1	0	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5030	5	4	10	16	9	10	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	41	9982	10	10	10	50	0	1	0	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5030	5	4	9	16	10	10	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	237	9982	10	10	10	50	0	1	0	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	1	0	5029	0	0	9	16	9	9	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	35	9982	10	10	10	50	0	0	5	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5031	0	0	9	16	9	9	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	77	0	0	0	766	9982	10	10	10	50	0	0	5	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5029	0	0	10	16	9	10	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	77	0	0	0	35	9982	10	10	10	50	0	0	5	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5028	5	4	10	16	10	9	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	78	0	21	0	35	9982	10	10	10	50	0	1	0	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5029	0	0	10	16	10	10	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	78	0	0	0	35	9982	10	10	10	50	0	1	0	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5029	0	0	10	16	9	11	10035	0	80010	10039	10039	10039	10039	10039
80024	10038	77	0	0	0	35	9982	10	10	10	50	0	0	5	49	6958	10038	10038	3	18	10	80020	80020	10038	35	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5029	5	4	10	16	9	8	10035	0	80010	10039	10039	10039	10039	10039

MOV (from sp, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations