Firestorm: CFINV measurements

Code:

  cfinv

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ld unit uop (a6)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	34	1	1	990	1000	1036	1036	1036	1036	1036
1004	1071	8	0	78	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	0	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	1000	0	12	73	1	27	1	1	990	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->1

Code:

  cfinv

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	21	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	10059	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	9	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	84	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	18	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	342	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	1	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	1	0	0	82	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	6	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	2	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	10100	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	12	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	18	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	21	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	6	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	108	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	2	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	1	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	204	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	2	27	3	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	84	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	3	27	3	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	294	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10010	0	0	640	3	27	2	3	9993	10010	10	10036	10036	10036	10036	10036

Test 3: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53444	400	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	2	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	138	88	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	15	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	1	2	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	1	1	0	0	702	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	399	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53460	53405	53405	53405	53405
160204	53404	400	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	8	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53390	400	0	0	0	0	0	0	0	0	0	328	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10022	13	3	1	31	19	2	1	1	14	11	53409	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10022	13	6	1	13	19	4	1	1	16	12	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	0	518	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	3	0	0	10022	13	6	1	15	19	2	1	1	19	13	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	0	91	25	160010	160010	160010	1029388	1	1	10	49	50485	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10022	13	6	1	14	19	2	1	1	14	11	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	3	0	0	10022	13	6	1	12	19	4	1	1	11	14	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10022	16	7	2	18	19	2	1	1	17	13	53370	160000	40	22	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10024	16	7	1	13	19	2	1	1	13	13	53370	160000	40	22	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	0	0	0	85	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10024	13	6	1	11	19	2	2	2	21	11	53370	160000	20	11	10	53471	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	39	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10022	13	6	1	13	19	4	2	2	13	19	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	0	0	0	708	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	10022	13	6	1	20	19	2	1	1	11	20	53370	160274	20	11	10	53375	53375	53375	53375	53375

Test 4: throughput

Count: 4

Code:

  fcmp s0, s0
  cfinv
  cfinv
  cfinv
  cfinv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13416	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	0	13432	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	3	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6128	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	0	13385	13414	13414	6128	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	15	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	0	13385	13414	13414	6128	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6128	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	399	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	2	2	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	0	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	0	0	3210	2	19	3	2	13411	40000	100	13415	13415	13415	13415	13415

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13408	101	2	0	0	0	0	0	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	0	0	3141	7	19	5	17	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	3	0	273	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	0	0	3141	17	19	7	17	13379	40000	10	13383	13383	13556	13477	13444
50024	13614	104	0	0	0	0	0	0	15	0	0	45	0	25	50010	40010	10000	40110	10000	573456	80000	0	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	510	0	3141	6	19	15	18	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	9	0	0	66	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	0	0	3141	17	19	5	17	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	0	0	3141	5	19	5	17	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	0	0	45	0	25	50102	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3230	3	7109	50010	40221	10000	40020	20000	13382	13441	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	0	0	3141	17	19	17	5	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	1	0	0	0	0	0	0	0	45	0	25	50010	40010	10000	40300	10049	573456	80000	0	13491	13382	13382	5504	3795	7	7205	50010	40312	10000	40020	20000	13551	13439	1	1	50021	10	9	10	40010	10000	10	4	2	2	0	0	1038	0	3141	7	42	5	17	13379	40214	10	13441	13383	13383	13383	13383
50024	13382	110	0	0	0	0	4	0	0	0	0	66	0	25	50010	40083	10000	40010	10117	573456	80760	0	13488	13382	13616	5575	3862	3	7109	50133	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	2	0	0	0	0	3141	17	19	17	6	13379	40000	10	13383	13383	13616	13441	13503
50024	13558	100	0	0	0	0	1	4	9	0	1	66	4	25	50010	40010	10000	40010	10000	573456	80000	0	13540	13382	13555	5575	3589	3	7109	50138	40305	10023	40020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	1830	0	3141	14	19	17	7	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	0	0	45	0	25	50010	40010	10098	40010	10000	582952	80000	0	13353	13382	13382	5864	3784	14	7109	50010	40020	10000	40414	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	0	0	0	3141	7	19	17	5	13379	40000	10	13383	13383	13383	13383	13383

CFINV

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations