Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldr x0, [x6, x7, lsl #3]
mov x7, #4 mov x8, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int load (95) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 399 | 2 | 1 | 1 | 0 | 0 | 0 | 65 | 1 | 0 | 0 | 385 | 2 | 18 | 21 | 16 | 25 | 1000 | 1000 | 1000 | 15331 | 0 | 399 | 400 | 222 | 3 | 258 | 1000 | 1000 | 2000 | 400 | 82 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1020 | 19 | 0 | 1060 | 1 | 0 | 1 | 65 | 1041 | 3 | 1 | 60 | 42 | 19 | 1 | 73 | 2 | 16 | 1 | 1 | 397 | 10 | 10 | 3 | 1000 | 401 | 400 | 401 | 401 | 400 |
| 1004 | 399 | 3 | 1 | 0 | 0 | 0 | 0 | 65 | 1 | 0 | 3 | 385 | 2 | 18 | 18 | 0 | 25 | 1000 | 1000 | 1000 | 15410 | 1 | 400 | 399 | 204 | 3 | 258 | 1000 | 1000 | 2000 | 399 | 64 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1019 | 19 | 42 | 1059 | 1 | 0 | 1 | 21 | 1000 | 3 | 1 | 19 | 42 | 19 | 0 | 73 | 1 | 16 | 1 | 1 | 397 | 0 | 10 | 3 | 1000 | 402 | 400 | 401 | 401 | 382 |
| 1004 | 400 | 3 | 1 | 1 | 1 | 0 | 1 | 65 | 1 | 0 | 1 | 385 | 2 | 18 | 0 | 17 | 25 | 1000 | 1000 | 1000 | 15423 | 0 | 400 | 400 | 222 | 3 | 258 | 1000 | 1000 | 2000 | 400 | 82 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1021 | 20 | 0 | 1019 | 1 | 0 | 1 | 21 | 1043 | 3 | 1 | 19 | 42 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 378 | 10 | 10 | 3 | 1000 | 401 | 382 | 383 | 401 | 401 |
| 1004 | 401 | 3 | 1 | 1 | 0 | 1 | 1 | 65 | 1 | 0 | 2 | 384 | 0 | 18 | 18 | 16 | 25 | 1000 | 1000 | 1000 | 14456 | 0 | 399 | 400 | 222 | 3 | 239 | 1000 | 1000 | 2000 | 400 | 64 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1019 | 21 | 42 | 1060 | 1 | 1 | 0 | 21 | 1041 | 0 | 1 | 60 | 42 | 19 | 2 | 73 | 1 | 16 | 1 | 1 | 397 | 10 | 0 | 3 | 1000 | 400 | 401 | 401 | 400 | 401 |
| 1004 | 381 | 3 | 1 | 1 | 0 | 0 | 0 | 65 | 0 | 0 | 2 | 384 | 2 | 18 | 18 | 16 | 25 | 1000 | 1000 | 1000 | 15382 | 1 | 399 | 400 | 222 | 3 | 258 | 1000 | 1000 | 2000 | 400 | 82 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1020 | 20 | 42 | 1060 | 1 | 0 | 1 | 62 | 1000 | 3 | 1 | 60 | 42 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 396 | 0 | 10 | 3 | 1000 | 401 | 401 | 401 | 401 | 401 |
| 1004 | 400 | 2 | 1 | 1 | 1 | 0 | 1 | 67 | 0 | 0 | 0 | 366 | 0 | 18 | 18 | 17 | 25 | 1000 | 1000 | 1000 | 15366 | 0 | 400 | 400 | 222 | 3 | 257 | 1000 | 1000 | 2000 | 400 | 64 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1020 | 20 | 42 | 1060 | 1 | 0 | 1 | 62 | 1041 | 3 | 1 | 19 | 42 | 19 | 2 | 73 | 1 | 16 | 1 | 1 | 384 | 10 | 0 | 2 | 1000 | 400 | 401 | 401 | 400 | 382 |
| 1004 | 382 | 2 | 1 | 1 | 1 | 0 | 0 | 65 | 1 | 0 | 2 | 385 | 0 | 18 | 0 | 17 | 25 | 1000 | 1000 | 1000 | 15423 | 0 | 381 | 399 | 222 | 3 | 258 | 1000 | 1000 | 2000 | 399 | 82 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1020 | 20 | 42 | 1062 | 1 | 0 | 1 | 62 | 1041 | 0 | 1 | 60 | 42 | 18 | 2 | 73 | 1 | 16 | 1 | 1 | 397 | 10 | 10 | 0 | 1000 | 401 | 401 | 401 | 400 | 401 |
| 1004 | 400 | 3 | 1 | 1 | 0 | 0 | 1 | 65 | 0 | 0 | 3 | 384 | 0 | 18 | 18 | 16 | 25 | 1000 | 1000 | 1000 | 14456 | 0 | 399 | 400 | 222 | 3 | 258 | 1000 | 1000 | 2000 | 400 | 82 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1020 | 19 | 42 | 1019 | 1 | 0 | 0 | 62 | 1000 | 3 | 1 | 60 | 0 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 396 | 10 | 10 | 0 | 1000 | 401 | 383 | 382 | 382 | 400 |
| 1004 | 399 | 3 | 1 | 1 | 1 | 0 | 1 | 65 | 0 | 0 | 2 | 384 | 2 | 18 | 0 | 0 | 25 | 1000 | 1000 | 1000 | 15563 | 1 | 401 | 381 | 222 | 3 | 258 | 1000 | 1000 | 2000 | 399 | 82 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1019 | 22 | 42 | 1061 | 1 | 0 | 1 | 62 | 1000 | 3 | 1 | 60 | 42 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 378 | 10 | 10 | 3 | 1000 | 401 | 404 | 383 | 401 | 383 |
| 1004 | 381 | 3 | 1 | 1 | 1 | 1 | 0 | 65 | 0 | 0 | 3 | 385 | 2 | 0 | 18 | 17 | 25 | 1000 | 1000 | 1000 | 15363 | 1 | 400 | 399 | 222 | 3 | 258 | 1000 | 1000 | 2000 | 400 | 64 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1019 | 19 | 0 | 1060 | 1 | 0 | 0 | 68 | 1043 | 3 | 1 | 19 | 42 | 19 | 1 | 73 | 1 | 16 | 1 | 1 | 378 | 0 | 10 | 3 | 1000 | 383 | 401 | 401 | 400 | 382 |
Chain cycles: 3
Code:
ldr x0, [x6, x7, lsl #3] eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x7, #4 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.0054
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 24 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40205 | 70054 | 524 | 0 | 0 | 0 | 0 | 1 | 0 | 2 | 1 | 0 | 0 | 0 | 70039 | 69785 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616159 | 3342110 | 0 | 49 | 66974 | 0 | 70054 | 70048 | 64659 | 3 | 64957 | 40100 | 30200 | 10000 | 60200 | 20000 | 70431 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 100 | 10003 | 2 | 1 | 10000 | 1 | 11 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 2610 | 3 | 71 | 2 | 2 | 69804 | 30006 | 7 | 0 | 7 | 10000 | 30100 | 70058 | 70055 | 70055 | 70042 | 70055 |
| 40204 | 70054 | 524 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 70039 | 69785 | 59713 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616068 | 3342398 | 0 | 49 | 66974 | 0 | 70054 | 70054 | 64650 | 3 | 65019 | 40100 | 30200 | 10000 | 60200 | 20000 | 70082 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10002 | 1 | 1 | 10002 | 0 | 1 | 1 | 4 | 10000 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 2610 | 2 | 71 | 2 | 2 | 69874 | 30006 | 0 | 0 | 7 | 10000 | 30100 | 70055 | 70055 | 70055 | 70042 | 70055 |
| 40204 | 70041 | 525 | 1 | 0 | 0 | 0 | 0 | 0 | 122 | 1 | 0 | 0 | 1 | 70033 | 69750 | 59707 | 25 | 40108 | 30103 | 10002 | 30100 | 10000 | 616078 | 3341769 | 0 | 49 | 66961 | 0 | 70054 | 70054 | 64650 | 3 | 64957 | 40100 | 30200 | 10000 | 60200 | 20000 | 70084 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10003 | 1 | 0 | 10001 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 2610 | 2 | 71 | 2 | 2 | 69804 | 30006 | 7 | 7 | 7 | 10000 | 30100 | 70055 | 70055 | 70055 | 70055 | 70055 |
| 40204 | 70041 | 525 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 70039 | 69785 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616078 | 3342398 | 0 | 49 | 66974 | 0 | 70041 | 70054 | 64650 | 3 | 64957 | 40100 | 30200 | 10000 | 60200 | 20000 | 70096 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 1 | 1 | 10002 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 2610 | 2 | 71 | 2 | 2 | 69817 | 30006 | 7 | 7 | 0 | 10000 | 30100 | 70055 | 70055 | 70055 | 70055 | 70055 |
| 40204 | 70054 | 524 | 1 | 0 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 70039 | 69785 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616041 | 3342398 | 1 | 49 | 66974 | 0 | 70054 | 70054 | 64650 | 3 | 64944 | 40100 | 30200 | 10000 | 60200 | 20000 | 70055 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10002 | 1 | 1 | 10003 | 0 | 0 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 2 | 1 | 0 | 2610 | 2 | 71 | 2 | 2 | 69817 | 30006 | 7 | 7 | 7 | 10000 | 30100 | 70055 | 70055 | 70055 | 70055 | 70055 |
| 40204 | 70041 | 525 | 1 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 1 | 70039 | 69702 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616041 | 3342398 | 0 | 98 | 66961 | 0 | 70115 | 70060 | 64650 | 3 | 64957 | 40100 | 30200 | 10000 | 60200 | 20000 | 70057 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 3 | 1 | 10002 | 0 | 0 | 2 | 1 | 10000 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 2610 | 2 | 71 | 2 | 2 | 69798 | 30003 | 0 | 7 | 10 | 10000 | 30100 | 70055 | 70055 | 70055 | 70055 | 70042 |
| 40204 | 70041 | 524 | 1 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 1 | 0 | 1 | 70039 | 69702 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616068 | 3342398 | 1 | 49 | 66974 | 0 | 70054 | 70054 | 64637 | 3 | 64957 | 40100 | 30200 | 10000 | 60200 | 20000 | 70085 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10002 | 2 | 1 | 10002 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 2 | 0 | 0 | 2610 | 2 | 71 | 2 | 2 | 69804 | 30006 | 0 | 7 | 7 | 10000 | 30100 | 70042 | 70055 | 70055 | 70055 | 70096 |
| 40204 | 70122 | 525 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 70026 | 69785 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616078 | 3342398 | 0 | 49 | 66968 | 0 | 70041 | 70054 | 64775 | 3 | 64951 | 40100 | 30200 | 10000 | 60200 | 20000 | 70054 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 3 | 1 | 10002 | 0 | 0 | 1 | 1 | 10000 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 2610 | 2 | 71 | 2 | 2 | 69817 | 30006 | 7 | 7 | 0 | 10000 | 30100 | 70055 | 70055 | 70042 | 70055 | 70042 |
| 40204 | 70054 | 525 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 70039 | 69785 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616041 | 3342398 | 0 | 49 | 66974 | 0 | 70054 | 70054 | 64650 | 3 | 64957 | 40100 | 30200 | 10000 | 60600 | 20000 | 70086 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 3 | 0 | 10003 | 0 | 7 | 2 | 1 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2610 | 2 | 71 | 2 | 2 | 69817 | 30003 | 7 | 7 | 7 | 10000 | 30100 | 70042 | 70042 | 70055 | 70055 | 70055 |
| 40204 | 70054 | 525 | 1 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 1 | 0 | 1 | 70039 | 69785 | 59713 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616041 | 3342398 | 0 | 49 | 66974 | 0 | 70041 | 70054 | 64650 | 3 | 64957 | 40100 | 30200 | 10000 | 60200 | 20000 | 70059 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 2 | 1 | 10001 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 0 | 1 | 2 | 0 | 0 | 2610 | 2 | 71 | 1 | 2 | 69810 | 30003 | 7 | 7 | 7 | 10000 | 30100 | 70049 | 70049 | 70049 | 70049 | 70055 |
Result (median cycles for code, minus 3 chain cycles): 4.0052
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 18 | 19 | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40025 | 70052 | 524 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 70037 | 69759 | 59715 | 25 | 40014 | 30010 | 10001 | 30010 | 10000 | 617068 | 3342302 | 1 | 49 | 66955 | 70035 | 70035 | 64670 | 0 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 20000 | 70055 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 14 | 10000 | 30010 | 70060 | 70053 | 70066 | 70053 | 70053 |
| 40024 | 70052 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70040 | 69780 | 59695 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617054 | 3342446 | 1 | 49 | 66955 | 70055 | 70052 | 64653 | 0 | 3 | 64980 | 40010 | 30020 | 10000 | 60020 | 20000 | 70035 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69818 | 30003 | 14 | 11 | 14 | 10000 | 30010 | 70038 | 70107 | 70055 | 70058 | 70053 |
| 40024 | 70052 | 524 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69780 | 59714 | 25 | 40010 | 30010 | 10000 | 30010 | 10000 | 617027 | 3342302 | 1 | 49 | 66955 | 70052 | 70055 | 64653 | 0 | 3 | 64980 | 40010 | 30020 | 10000 | 60020 | 20000 | 70055 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 3 | 10000 | 0 | 0 | 2520 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 14 | 14 | 10000 | 30010 | 70076 | 70054 | 70056 | 70056 | 70056 |
| 40024 | 70055 | 524 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69787 | 59714 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617000 | 3342446 | 1 | 49 | 66975 | 70052 | 70052 | 64670 | 0 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 20000 | 70055 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30010 | 70068 | 70040 | 70057 | 70039 | 70053 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69782 | 59714 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617000 | 3342446 | 1 | 49 | 66975 | 70055 | 70035 | 64670 | 0 | 3 | 64980 | 40010 | 30020 | 10000 | 60020 | 20000 | 70052 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69818 | 30003 | 11 | 14 | 14 | 10000 | 30010 | 70116 | 70043 | 70398 | 70059 | 70053 |
| 40024 | 70035 | 524 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70020 | 69776 | 59711 | 25 | 40014 | 30010 | 10001 | 30010 | 10000 | 617000 | 3342302 | 1 | 49 | 66972 | 70055 | 70052 | 64673 | 0 | 3 | 64980 | 40010 | 30020 | 10000 | 60020 | 20000 | 70052 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 2520 | 2 | 71 | 1 | 1 | 69815 | 30003 | 11 | 14 | 11 | 10000 | 30010 | 70092 | 70055 | 70060 | 70053 | 70036 |
| 40024 | 70055 | 524 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70037 | 69783 | 59714 | 25 | 40022 | 30013 | 10001 | 30010 | 10000 | 617068 | 3342446 | 1 | 49 | 66972 | 70035 | 70052 | 64670 | 0 | 3 | 64980 | 40010 | 30020 | 10000 | 60020 | 20000 | 70060 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 0 | 0 | 10000 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69818 | 30000 | 0 | 14 | 0 | 10000 | 30010 | 70101 | 70053 | 70056 | 70053 | 70053 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70020 | 69781 | 59711 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617068 | 3342446 | 1 | 49 | 66975 | 70052 | 70052 | 64653 | 0 | 3 | 64977 | 40010 | 30020 | 10000 | 60020 | 20000 | 70055 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2520 | 2 | 71 | 1 | 1 | 69818 | 30003 | 0 | 14 | 0 | 10000 | 30010 | 70087 | 70056 | 70058 | 70056 | 70056 |
| 40024 | 70052 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69786 | 59714 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617000 | 3342446 | 1 | 49 | 66972 | 70052 | 70055 | 64673 | 0 | 3 | 64960 | 40010 | 30020 | 10000 | 60020 | 20000 | 70055 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69815 | 30003 | 14 | 11 | 11 | 10000 | 30010 | 70058 | 70042 | 70056 | 70036 | 70053 |
| 40024 | 70035 | 524 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70040 | 69827 | 59711 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617027 | 3341518 | 1 | 49 | 66977 | 70035 | 70055 | 64673 | 0 | 3 | 64980 | 40010 | 30020 | 10000 | 60020 | 20000 | 70055 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69815 | 30003 | 14 | 11 | 14 | 10000 | 30010 | 70416 | 70057 | 70091 | 70055 | 70053 |
Chain cycles: 3
Code:
ldr x0, [x6, x7, lsl #3] eor x8, x8, x0 eor x8, x8, x0 add x7, x7, x8
mov x7, #4 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.0052
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 18 | 19 | 1e | 22 | 24 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40205 | 70052 | 524 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 70037 | 69783 | 59711 | 25 | 40104 | 30103 | 10013 | 30100 | 10000 | 616023 | 3342302 | 0 | 49 | 66975 | 70052 | 70052 | 64648 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70127 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 3 | 10000 | 1 | 1 | 0 | 2610 | 2 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 524 | 0 | 0 | 3 | 0 | 1 | 1 | 0 | 70039 | 69783 | 59713 | 122 | 40104 | 30103 | 10001 | 30100 | 10000 | 616023 | 3342302 | 0 | 49 | 66972 | 70052 | 70035 | 64631 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70113 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 524 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69783 | 59695 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616023 | 3342302 | 1 | 49 | 66972 | 70052 | 70052 | 64648 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70093 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69783 | 59711 | 25 | 40104 | 30103 | 10001 | 30100 | 10204 | 616041 | 3342302 | 0 | 49 | 66972 | 70052 | 70035 | 64648 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70057 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 17 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70036 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 524 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69783 | 59711 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616023 | 3342302 | 0 | 49 | 66972 | 70052 | 70052 | 64648 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70093 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69817 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69783 | 59711 | 25 | 40104 | 30103 | 10000 | 30100 | 10000 | 616023 | 3342302 | 0 | 49 | 66972 | 70052 | 70052 | 64648 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70107 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69783 | 59711 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616023 | 3342302 | 0 | 49 | 66975 | 70414 | 70052 | 64650 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70093 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69783 | 59711 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616175 | 3342302 | 0 | 49 | 66972 | 70052 | 70052 | 64648 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70098 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 524 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70020 | 69781 | 59711 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616023 | 3342302 | 1 | 49 | 66972 | 70052 | 70052 | 64648 | 3 | 64961 | 40100 | 30200 | 10000 | 60200 | 20000 | 70090 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10003 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30000 | 11 | 11 | 11 | 10000 | 30100 | 70053 | 70053 | 70053 | 70053 | 70053 |
| 40204 | 70052 | 524 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70037 | 69783 | 59711 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616023 | 3342302 | 1 | 49 | 66972 | 70052 | 70052 | 64648 | 3 | 64955 | 40100 | 30200 | 10000 | 60200 | 20000 | 70106 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 3 | 10006 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30003 | 11 | 11 | 11 | 10000 | 30100 | 70058 | 70053 | 70053 | 70036 | 70053 |
Result (median cycles for code, minus 3 chain cycles): 4.0058
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40025 | 70041 | 525 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 70046 | 69782 | 59701 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 617013 | 3342734 | 0 | 49 | 66981 | 70041 | 70058 | 64659 | 3 | 64986 | 40010 | 30020 | 10000 | 60020 | 20000 | 70061 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10003 | 1 | 1 | 10003 | 0 | 0 | 0 | 22 | 10000 | 1 | 1 | 1 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69821 | 30006 | 11 | 11 | 0 | 10000 | 30010 | 70042 | 70062 | 70042 | 70060 | 70062 |
| 40024 | 70041 | 525 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 70026 | 69785 | 59763 | 25 | 40014 | 30016 | 10001 | 30010 | 10000 | 616995 | 3342734 | 0 | 49 | 66978 | 70061 | 70061 | 64679 | 3 | 64987 | 40010 | 30020 | 10000 | 60020 | 20000 | 70041 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10002 | 1 | 0 | 10001 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 2520 | 1 | 71 | 1 | 1 | 69882 | 30003 | 14 | 14 | 14 | 10000 | 30010 | 70042 | 70042 | 70062 | 70062 | 70059 |
| 40024 | 70041 | 524 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 26 | 88 | 0 | 0 | 0 | 70043 | 69789 | 59720 | 25 | 40018 | 30016 | 10001 | 30010 | 10000 | 617054 | 3341769 | 0 | 49 | 66978 | 70061 | 70078 | 64679 | 3 | 64983 | 40010 | 30020 | 10000 | 60020 | 20000 | 70061 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10002 | 1 | 1 | 10001 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 0 | 1 | 0 | 2520 | 1 | 71 | 1 | 2 | 69821 | 30006 | 14 | 14 | 14 | 10000 | 30010 | 70062 | 70062 | 70044 | 70059 | 70064 |
| 40024 | 70041 | 525 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 70043 | 69702 | 59720 | 25 | 40018 | 30016 | 10001 | 30010 | 10000 | 617054 | 3341769 | 0 | 49 | 66981 | 70041 | 70041 | 64659 | 3 | 64986 | 40010 | 30020 | 10000 | 60020 | 20000 | 70061 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10001 | 2 | 1 | 10002 | 0 | 0 | 0 | 4 | 10000 | 1 | 1 | 0 | 1 | 1 | 2520 | 1 | 71 | 1 | 1 | 69824 | 30006 | 14 | 0 | 0 | 10000 | 30010 | 70062 | 70042 | 70059 | 70042 | 70138 |
| 40024 | 70058 | 524 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 70043 | 69785 | 59722 | 25 | 40014 | 30027 | 10002 | 30010 | 10000 | 617081 | 3341769 | 0 | 49 | 66961 | 70041 | 70041 | 64659 | 3 | 64986 | 40010 | 30020 | 10000 | 60020 | 20000 | 70058 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10001 | 1 | 1 | 10003 | 0 | 0 | 2 | 4 | 10000 | 1 | 1 | 1 | 1 | 1 | 2544 | 1 | 71 | 1 | 1 | 69821 | 30017 | 11 | 14 | 14 | 10000 | 30010 | 70067 | 70063 | 70154 | 70066 | 70044 |
| 40024 | 70063 | 525 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 52 | 0 | 1 | 0 | 0 | 70043 | 69785 | 59701 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 616995 | 3341769 | 0 | 49 | 66978 | 70061 | 70061 | 64676 | 3 | 64986 | 40010 | 30183 | 10000 | 60020 | 20000 | 70058 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10001 | 1 | 0 | 10002 | 0 | 12 | 0 | 4 | 10000 | 1 | 1 | 1 | 1 | 2 | 2520 | 1 | 71 | 1 | 1 | 69821 | 30003 | 11 | 0 | 14 | 10000 | 30010 | 70061 | 70062 | 70062 | 70062 | 70059 |
| 40024 | 70049 | 524 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 70044 | 69782 | 59722 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 617081 | 3341769 | 0 | 49 | 66978 | 70058 | 70058 | 64679 | 3 | 64983 | 40010 | 30020 | 10000 | 60020 | 20000 | 70041 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10003 | 2 | 0 | 10001 | 0 | 3 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 2520 | 1 | 71 | 1 | 1 | 69826 | 30003 | 14 | 14 | 14 | 10000 | 30010 | 70059 | 70042 | 70042 | 70062 | 70059 |
| 40024 | 70061 | 524 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 70026 | 69785 | 59720 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 617090 | 3345554 | 0 | 49 | 66981 | 70154 | 70041 | 64679 | 3 | 64986 | 40010 | 30020 | 10000 | 60020 | 20000 | 70058 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10002 | 2 | 0 | 10001 | 0 | 0 | 1 | 1 | 10000 | 1 | 1 | 0 | 1 | 0 | 2544 | 1 | 71 | 1 | 1 | 69804 | 30006 | 0 | 14 | 0 | 10000 | 30010 | 70059 | 70062 | 70062 | 70062 | 70062 |
| 40024 | 70041 | 524 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 70046 | 69782 | 59701 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 616995 | 3341769 | 0 | 49 | 66978 | 70061 | 70066 | 64664 | 3 | 64987 | 40010 | 30020 | 10000 | 60344 | 20000 | 70061 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10001 | 1 | 1 | 10002 | 0 | 0 | 1 | 2318 | 10000 | 1 | 1 | 1 | 1 | 0 | 2520 | 1 | 71 | 1 | 1 | 69810 | 30006 | 14 | 11 | 0 | 10000 | 30010 | 70059 | 70042 | 70062 | 70062 | 70042 |
| 40024 | 70058 | 525 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 70046 | 69785 | 59717 | 25 | 40018 | 30013 | 10002 | 30010 | 10000 | 617063 | 3342590 | 0 | 49 | 66981 | 70061 | 70058 | 64679 | 3 | 64986 | 40010 | 30020 | 10000 | 60020 | 20000 | 70041 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10002 | 1 | 1 | 10002 | 0 | 0 | 2 | 1 | 10000 | 0 | 1 | 1 | 1 | 0 | 2520 | 1 | 71 | 1 | 1 | 69821 | 30006 | 14 | 0 | 0 | 10000 | 30010 | 70042 | 70062 | 70059 | 70062 | 70059 |
Count: 8
Code:
ldr x0, [x6, x7, lsl #3] ldr x0, [x6, x7, lsl #3] ldr x0, [x6, x7, lsl #3] ldr x0, [x6, x7, lsl #3] ldr x0, [x6, x7, lsl #3] ldr x0, [x6, x7, lsl #3] ldr x0, [x6, x7, lsl #3] ldr x0, [x6, x7, lsl #3]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3339
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 19 | 1e | 3a | 3f | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bb | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80205 | 26715 | 200 | 1 | 1 | 1 | 1 | 0 | 21 | 2 | 26699 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166590 | 1 | 49 | 23634 | 26715 | 26714 | 16642 | 6 | 16666 | 80116 | 200 | 80024 | 200 | 160048 | 26716 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80020 | 20 | 0 | 80019 | 1 | 0 | 1 | 21 | 80000 | 19 | 19 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 0 | 0 | 26711 | 80000 | 100 | 26715 | 26715 | 26715 | 26715 | 26716 |
| 80204 | 26714 | 200 | 1 | 1 | 0 | 1 | 0 | 21 | 1 | 26699 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166590 | 0 | 49 | 23634 | 26714 | 26714 | 16642 | 6 | 16666 | 80116 | 200 | 80024 | 200 | 160048 | 26722 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80020 | 19 | 0 | 80019 | 1 | 0 | 2 | 21 | 80000 | 19 | 19 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26711 | 80000 | 100 | 26715 | 26715 | 26715 | 26715 | 26715 |
| 80204 | 26714 | 200 | 1 | 1 | 0 | 1 | 0 | 21 | 2 | 26699 | 0 | 1 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1167215 | 0 | 49 | 23634 | 26714 | 26714 | 16642 | 6 | 16666 | 80115 | 200 | 80024 | 200 | 160048 | 26915 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80019 | 21 | 0 | 80019 | 2 | 0 | 0 | 21 | 80000 | 19 | 19 | 2 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26718 | 80000 | 100 | 26715 | 26717 | 26715 | 26715 | 26715 |
| 80204 | 26714 | 200 | 1 | 0 | 1 | 0 | 0 | 21 | 1 | 26699 | 0 | 1 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166836 | 0 | 49 | 23634 | 26714 | 26714 | 16642 | 6 | 16666 | 80115 | 200 | 80024 | 200 | 160048 | 26886 | 65 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80020 | 21 | 0 | 80019 | 0 | 0 | 0 | 21 | 80000 | 19 | 19 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26711 | 80000 | 100 | 26715 | 26715 | 26715 | 26715 | 26715 |
| 80204 | 26714 | 200 | 1 | 1 | 1 | 1 | 0 | 21 | 1 | 26699 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80016 | 500 | 1166590 | 0 | 49 | 23634 | 26714 | 26715 | 16642 | 6 | 16666 | 80115 | 200 | 80024 | 200 | 160048 | 26719 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80151 | 20 | 0 | 80019 | 2 | 0 | 0 | 21 | 80000 | 19 | 19 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26711 | 80000 | 100 | 26715 | 26715 | 26715 | 26715 | 26715 |
| 80204 | 26714 | 200 | 1 | 1 | 0 | 0 | 0 | 21 | 1 | 26699 | 0 | 1 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166836 | 0 | 49 | 23634 | 26805 | 26714 | 16642 | 6 | 16666 | 80115 | 200 | 80024 | 200 | 160048 | 26723 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80020 | 20 | 0 | 80019 | 0 | 0 | 2 | 21 | 80000 | 19 | 19 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26711 | 80000 | 100 | 26715 | 26716 | 26715 | 26715 | 26715 |
| 80204 | 26714 | 200 | 1 | 1 | 1 | 1 | 0 | 21 | 1 | 26699 | 0 | 1 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166836 | 0 | 49 | 23634 | 26714 | 26714 | 16642 | 6 | 16666 | 80115 | 200 | 80024 | 200 | 160048 | 26723 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80021 | 21 | 0 | 80019 | 1 | 0 | 0 | 21 | 80000 | 19 | 19 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26711 | 80000 | 100 | 26715 | 26715 | 26715 | 26715 | 26715 |
| 80204 | 26714 | 200 | 1 | 1 | 1 | 1 | 0 | 21 | 2 | 26699 | 0 | 1 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1167203 | 1 | 49 | 23634 | 26714 | 26714 | 16642 | 6 | 16666 | 80115 | 200 | 80024 | 200 | 160048 | 27167 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80021 | 19 | 0 | 80019 | 0 | 0 | 0 | 21 | 80000 | 19 | 19 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26711 | 80000 | 100 | 26715 | 26715 | 26715 | 26715 | 26716 |
| 80204 | 26715 | 200 | 1 | 0 | 1 | 1 | 0 | 21 | 1 | 26699 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80021 | 500 | 1166164 | 1 | 49 | 23634 | 26714 | 26714 | 16635 | 9 | 16655 | 80119 | 200 | 80030 | 200 | 160060 | 26842 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80542 | 20 | 0 | 80019 | 1 | 0 | 1 | 21 | 80000 | 19 | 19 | 1 | 2 | 2 | 2 | 5128 | 1 | 23 | 1 | 1 | 26711 | 80000 | 100 | 26716 | 26715 | 26715 | 26715 | 26715 |
| 80204 | 26714 | 200 | 1 | 1 | 1 | 1 | 0 | 21 | 2 | 26699 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80020 | 500 | 1166467 | 0 | 49 | 23634 | 26714 | 26714 | 16632 | 9 | 16655 | 80121 | 200 | 80030 | 200 | 160060 | 26748 | 64 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80019 | 20 | 0 | 80019 | 0 | 1 | 0 | 21 | 80000 | 19 | 19 | 0 | 2 | 2 | 2 | 5129 | 1 | 23 | 1 | 1 | 26714 | 80000 | 100 | 26715 | 26715 | 26715 | 26715 | 26716 |
Result (median cycles for code divided by count): 0.3338
| retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk data (08) | 1e | 22 | 3a | 3f | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | bb | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80025 | 26708 | 200 | 0 | 0 | 0 | 0 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16652 | 3 | 16815 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 5024 | 11 | 16 | 8 | 17 | 26708 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 1 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16652 | 3 | 16750 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 1 | 5024 | 15 | 16 | 16 | 14 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16652 | 3 | 16747 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 5024 | 16 | 16 | 16 | 16 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26710 | 200 | 0 | 0 | 0 | 0 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16652 | 3 | 16758 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 5024 | 13 | 16 | 13 | 17 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 43 | 0 | 5024 | 17 | 16 | 16 | 14 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26795 | 26708 | 16652 | 3 | 16775 | 80010 | 20 | 80000 | 20 | 160000 | 26708 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 5024 | 13 | 16 | 16 | 14 | 26705 | 80000 | 10 | 26712 | 26709 | 26709 | 26709 | 26712 |
| 80024 | 26708 | 200 | 0 | 1 | 0 | 0 | 2 | 26696 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16656 | 3 | 16690 | 80010 | 20 | 80000 | 20 | 160000 | 26718 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 2 | 0 | 80000 | 0 | 0 | 0 | 5096 | 16 | 24 | 15 | 21 | 26854 | 80000 | 10 | 26744 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 12 | 1 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26726 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 5024 | 11 | 16 | 16 | 14 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 49 | 23628 | 26708 | 26708 | 16652 | 3 | 16691 | 80010 | 20 | 80000 | 20 | 160000 | 26724 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 5024 | 16 | 16 | 14 | 16 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 2 | 26693 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1170044 | 49 | 23631 | 26712 | 26711 | 16652 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26720 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 5024 | 14 | 16 | 18 | 19 | 26705 | 80000 | 10 | 26709 | 26709 | 26709 | 26709 | 26709 |