Firestorm: MSR (SSBS) measurements

Code:

  msr s3_3_c4_c2_6, x0

Initialization

  mrs x0, s3_3_c4_c2_6

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	51	60	69	6a	6d	6e	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
4004	30026	233	0	0	129	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027
4004	30026	232	0	0	39	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30049	30027	30027
4004	30026	233	0	0	327	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027
4004	30026	233	0	0	15	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027
4004	30026	232	0	0	6	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19072	1	1	30023	30027	30027	30027	30027	30027
4004	30026	233	0	0	21	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027
4004	30026	232	0	0	6	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027
4004	30026	232	0	0	354	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027
4004	30026	232	0	0	15	30011	28024	0	49	26946	30026	30026	3003	10010	30026	30026	1001	1001	1001	0	0	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027
4004	30026	232	0	0	117	30011	28024	1	49	26946	30026	30026	3015	10010	30026	30026	1001	1001	1001	0	1	0	6006	1	19013	1	1	30023	30027	30027	30027	30027	30027

Code:

  msr s3_3_c4_c2_6, x0

Initialization

  mrs x0, s3_3_c4_c2_6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 30.0831

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
40204	300839	2332	0	0	0	0	0	12	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	1	1	1	60112	0	0	190021	0	0	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	0	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	1	0	3	1	1	1	60112	0	0	190021	0	2	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	0	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	1	0	3	1	1	1	60112	0	0	190021	0	0	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	0	0	0	300816	279931	100	100	100	500	0	49	294703	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	1	1	1	60112	0	1	190021	1	0	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	12	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	1	0	0	1	1	1	60112	0	0	190021	0	0	300828	100	300944	301073	300832	300832	300832
40204	300831	2332	0	1	1	0	0	0	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	301016	301108	10002	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	1	1	1	60112	0	0	190021	1	0	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	3	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	1	1	1	60112	0	0	190021	0	0	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	12	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	1	1	1	60112	0	0	190021	0	0	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	0	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	1	1	1	60112	0	0	190021	0	0	300828	100	300832	300832	300832	300832	300832
40204	300831	2332	0	0	0	0	0	0	0	0	300816	279931	100	100	100	500	0	49	297751	0	300831	300831	30006	100703	100	200	200	300831	300831	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	1	1	1	60112	0	0	190021	2	0	300828	100	300832	300832	300832	300832	300832

1000 unrolls and 10 iterations

Result (median cycles for code): 30.0107

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
40024	300115	2326	0	0	0	0	0	12	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	1	0	0	0	0	60015	87	190015	51	50	300104	10	300108	300108	300108	300108	300108
40024	300107	2326	1	0	0	0	0	12	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	60015	50	190015	51	49	300104	10	300108	300108	300108	300108	300108
40024	300107	2326	0	0	0	0	0	12	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	1	0	0	0	0	60014	50	190015	50	44	300104	10	300108	300108	300108	300108	300108
40024	300107	2326	0	0	0	0	0	0	0	0	300092	280015	10	10	10	50	1	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	60015	50	190015	50	50	300104	10	300108	300108	300108	300108	300108
40024	300107	2326	0	0	0	0	0	0	0	0	300092	280015	10	10	10	50	0	49	297279	300107	300107	30006	100142	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	60015	50	190015	51	50	300104	10	300294	300564	300464	300108	300108
40024	300107	2327	0	0	0	0	0	9	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	0	0	3	0	0	60015	50	190015	50	50	300104	10	300108	300108	300108	300108	300108
40024	300107	2326	1	0	0	0	0	0	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	60015	50	190015	51	50	300104	10	300108	300108	300108	300108	300108
40024	300107	2326	0	0	0	0	0	0	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	60015	50	190015	51	50	300104	10	300108	300108	300108	300108	300108
40024	300107	2326	0	0	0	0	0	0	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	1	0	0	0	0	60015	50	190015	50	50	300104	10	300108	300108	300108	300108	300108
40024	300107	2327	0	0	0	0	0	0	0	0	300092	280015	10	10	10	50	0	49	297027	300107	300107	30003	100081	10	20	20	300107	300107	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	60015	50	190015	50	52	300104	10	300108	300108	300108	300108	300108

MSR (SSBS)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations