Firestorm: LDR (register, sxtw, 32-bit) measurements

Code:

  ldr w0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	2	1	1	1	0	1	21	1	0	2	383	2	18	18	15	25	1000	1000	1000	15421	1	399	384	204	3	257	1000	1000	2000	381	81	1	1	1001	1000	1000	0	1020	21	42	1057	1	0	0	59	1037	6	0	57	42	19	0	73	2	16	2	2	396	9	9	2	1000	400	400	400	400	399
1004	399	3	1	0	1	0	0	65	0	0	3	384	0	0	18	0	25	1000	1000	1000	14533	0	399	398	222	3	240	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1020	21	42	1019	0	0	0	59	1038	0	1	57	0	19	0	73	2	16	2	2	379	9	9	2	1000	400	418	382	400	399
1004	399	3	1	1	1	0	0	21	1	0	1	384	2	0	18	0	25	1000	1000	1000	15334	0	399	398	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1020	19	0	1057	1	0	2	58	1038	6	1	57	42	19	0	73	2	16	2	2	400	9	9	2	1000	400	382	382	400	403
1004	399	2	1	1	0	0	0	21	1	0	2	384	2	18	18	0	25	1000	1000	1000	14456	1	399	398	204	3	239	1000	1000	2000	399	82	1	1	1001	1000	1000	0	1019	20	0	1058	1	0	1	62	1000	0	0	57	42	19	1	73	2	16	2	2	396	9	9	0	1000	382	382	400	399	399
1004	399	3	1	1	1	0	0	21	1	0	3	384	2	18	18	0	25	1000	1000	1000	14399	1	398	399	204	3	260	1000	1000	2000	399	64	1	1	1001	1000	1000	0	1020	21	0	1057	1	0	0	21	1039	6	1	56	42	19	1	73	2	16	2	2	396	9	9	0	1000	400	400	399	399	399
1004	399	3	1	0	1	0	0	65	1	0	2	384	1	18	18	16	25	1000	1000	1000	15349	0	398	381	221	3	256	1000	1000	2000	399	64	1	1	1001	1000	1000	0	1020	20	42	1019	0	0	0	59	1000	6	1	57	42	19	0	73	2	16	2	2	378	9	9	2	1000	399	399	399	399	400
1004	382	3	1	1	0	0	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15323	1	399	399	222	3	257	1000	1000	2000	398	64	1	1	1001	1000	1000	0	1021	20	42	1056	0	0	0	21	1000	6	1	56	42	19	0	73	2	16	2	2	379	0	9	0	1000	382	383	383	383	387
1004	399	3	1	0	0	0	0	21	0	0	2	384	0	18	18	0	25	1000	1000	1000	15375	0	399	399	221	3	257	1000	1000	2000	382	82	1	1	1001	1000	1000	0	1019	19	42	1057	1	0	1	62	1038	6	1	57	0	19	2	73	2	16	2	2	378	0	9	0	1000	382	399	382	400	385
1004	406	3	1	1	1	0	0	65	1	0	2	366	0	0	18	0	25	1000	1000	1000	15318	0	399	399	204	3	256	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1020	19	0	1019	1	0	1	21	1038	6	1	19	42	19	1	73	2	16	2	2	378	9	9	2	1000	400	382	399	383	383
1004	399	2	1	0	1	0	0	65	1	0	1	366	2	18	0	0	25	1000	1000	1000	14456	1	399	382	221	3	257	1000	1000	2000	399	64	1	1	1001	1000	1000	1	1020	20	42	1057	1	0	0	59	1038	6	0	57	42	19	2	73	2	16	2	2	378	0	0	2	1000	382	400	400	400	400

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	0	1	1	1	1	0	0	70032	69764	59709	25	40104	30103	10001	30100	10000	616005	3342206	0	0	49	66955	0	70050	70047	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2611	2	71	3	2	69813	30003	9	6	6	10000	30100	70048	70036	70051	70051	70048
40204	70035	525	0	0	0	0	1	0	0	70032	69781	59709	25	40104	30103	10001	30100	10000	616005	3342206	0	0	49	66967	0	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2611	3	71	3	3	69810	30003	0	6	9	10000	30100	70048	70051	70051	70051	70051
40204	70047	525	0	0	0	0	13	1	0	70035	69764	59695	25	40100	30103	10001	30100	10000	616175	3341470	0	0	49	66967	0	70050	70050	64646	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2611	3	71	2	3	69813	30003	0	6	6	10000	30100	70051	70051	70051	70051	70048
40204	70035	525	0	0	0	0	1	0	0	70032	69781	59709	25	40104	30103	10000	30100	10000	616175	3342206	0	0	49	66967	0	70035	70035	64643	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	0	0	2611	3	71	3	3	69813	30003	0	6	0	10000	30100	70051	70036	70051	70051	70036
40204	70050	524	0	0	0	0	1	0	0	70032	69764	59709	25	40104	30103	10001	30100	10000	616005	3341470	0	0	49	66967	0	70047	70047	64646	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	0	0	2611	2	71	2	3	69798	30003	0	6	9	10000	30100	70051	70051	70048	70037	70090
40204	70050	525	0	0	0	0	1	0	0	70032	69781	59695	25	40100	30103	10001	30100	10000	616005	3342062	0	0	49	66955	0	70035	70035	64643	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2611	2	71	3	3	69798	30000	9	6	6	10000	30100	70048	70048	70048	70048	70051
40204	70047	524	1	0	0	0	1	0	0	70032	69781	59709	25	40104	30100	10000	30100	10000	616005	3342206	0	0	49	66955	0	70035	70050	64646	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2611	3	71	3	3	69798	30000	0	6	6	10000	30100	70051	70051	70048	70036	70051
40204	70035	524	0	0	0	0	1	0	0	70020	69764	59706	25	40100	30103	10001	30100	10000	616175	3342206	0	0	49	66955	0	70047	70047	64646	3	64950	40310	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2611	3	71	3	2	69810	30003	0	0	6	10000	30100	70048	70051	70051	70051	70048
40204	70049	525	0	0	1	1	1	0	0	70032	69767	59709	25	40104	30103	10000	30100	10000	616005	3342206	0	0	49	66955	0	70035	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2611	3	71	3	3	69798	30000	9	9	6	10000	30100	70051	70051	70048	70051	70051
40204	70050	525	0	0	0	0	0	0	1	70117	69781	59706	25	40104	30103	10000	30100	10000	616005	3342062	0	0	49	66970	0	70035	70050	64631	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2611	2	71	3	2	69810	30003	9	6	9	10000	30100	70051	70036	70051	70092	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	0	0	0	0	0	0	0	0	1	0	1	0	0	70032	69760	59709	25	40014	30010	10001	30010	10058	616952	3342062	0	49	66970	70047	70050	64670	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	1	0	0	2520	2	71	1	1	69836	30003	6	0	9	10000	30010	70051	70048	70036	70036	70051
40024	70050	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70035	69760	59709	25	40010	30013	10001	30010	10000	616982	3342206	0	49	66970	70047	70050	64653	3	64960	40010	30215	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	1	0	0	2520	1	71	1	1	69817	30003	6	6	9	10000	30010	70053	70048	70051	70051	70048
40024	70050	524	0	0	0	0	0	0	0	0	1	0	1	0	0	70020	69763	59709	25	40014	30013	10000	30010	10000	617027	3342206	0	49	66970	70035	70047	64653	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	2520	1	71	1	1	69829	30000	9	9	0	10000	30010	70051	70051	70036	70048	70051
40024	70047	524	0	0	0	0	0	0	0	0	1	0	1	0	0	70035	69760	59709	25	40014	30013	10001	30010	10000	617027	3341470	0	49	66970	70035	70050	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	0	0	0	2520	1	71	1	1	69848	30003	0	6	0	10000	30010	70051	70048	70036	70036	70036
40024	70035	525	0	0	0	0	0	0	0	0	1	0	1	0	0	70035	69730	59709	25	40014	30010	10001	30010	10000	616952	3342206	0	49	66967	70047	70050	64665	3	64960	40010	30020	10000	60020	20000	70052	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	1	0	0	2520	0	71	1	2	69806	30003	0	0	9	10000	30010	70036	70036	70051	70036	70051
40024	70050	525	0	0	0	0	0	0	0	0	0	0	0	0	0	70032	69760	59706	25	40014	30013	10001	30010	10000	616982	3341470	0	49	66967	70050	70047	64665	3	64962	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	1	0	0	2520	1	71	1	1	69848	30003	6	0	0	10000	30010	70048	70051	70056	70051	70048
40024	70050	525	0	0	0	0	0	0	0	0	6	0	0	0	0	70035	69743	59706	25	40014	30010	10000	30010	10000	617068	3342062	0	49	66975	70050	70050	64653	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	1	2520	1	71	1	1	69865	30003	9	9	9	10000	30010	70051	70048	70051	70048	70036
40024	70047	525	0	0	0	0	0	0	0	0	1	0	1	0	0	70035	69743	59706	25	40014	30010	10001	30010	10000	616982	3342206	0	49	66970	70050	70050	64665	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	1	0	0	10000	1	0	0	0	2520	1	71	1	1	69846	30003	9	0	9	10000	30010	70036	70036	70036	70036	70036
40024	70050	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70035	69743	59695	25	40010	30010	10001	30010	10000	616982	3342206	0	98	66955	70050	70050	64668	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	0	1	0	0	2520	1	71	1	1	69817	30000	0	0	9	10000	30010	70051	70051	70051	70036	70051
40024	70050	525	0	0	0	0	0	0	0	0	6	0	1	0	0	70035	69779	59709	25	40014	30013	10000	30010	10000	616952	3341470	0	49	66970	70035	70047	64653	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	1	0	0	10000	0	1	0	0	2520	1	71	1	1	69860	30003	9	0	0	10000	30010	70051	70051	70051	70036	70051

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	0	0	0	0	0	0	0	0	1	0	0	70045	69782	59713	25	40104	30103	10001	30100	10000	616014	3342398	1	49	66974	70054	70054	64650	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69798	30003	13	0	13	10000	30100	70055	70055	70052	70052	70036
40204	70051	525	0	0	0	0	0	0	1	0	0	0	0	70049	69782	59713	25	40104	30103	10000	30100	10000	616014	3342398	1	49	66974	70051	70056	64650	3	64957	40100	30200	10000	60200	20000	70125	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	1	0	2610	1	71	1	1	69817	30003	0	10	10	10000	30100	70055	70055	70055	70055	70088
40204	70054	525	0	0	0	0	1	2	0	0	0	0	0	70036	69785	59713	25	40100	30103	10001	30100	10000	616041	3342254	1	49	66974	70035	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69817	30003	13	13	13	10000	30100	70036	70055	70052	70052	70055
40204	70054	525	0	1	0	0	0	0	0	0	0	0	0	70039	69782	59713	25	40104	30103	10001	30100	10000	616014	3342398	1	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69798	30003	13	13	13	10000	30100	70055	70055	70055	70055	70036
40204	70054	525	0	0	0	0	0	0	1	0	0	0	0	70039	69782	59713	25	40104	30103	10001	30100	10000	616041	3342398	1	49	67009	70054	70059	64631	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69817	30003	10	10	10	10000	30100	70055	70055	70052	70055	70055
40204	70051	525	0	0	0	0	0	0	1	0	0	0	0	70043	69764	59713	25	40104	30103	10001	30100	10000	616041	3342638	1	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	0	1	0	2610	1	71	1	1	69814	30003	13	10	0	10000	30100	70055	70036	70055	70055	70055
40204	70054	525	0	0	0	0	0	0	1	0	1	0	0	70082	69782	59695	25	40104	30103	10001	30100	10000	616014	3342398	1	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	17	1	1	69798	30059	10	10	13	10000	30100	70056	70055	70145	70229	70055
40204	70054	525	0	0	0	0	0	0	1	0	0	0	0	70039	69785	59713	25	40104	30100	10001	30100	10000	616014	3342398	0	49	66979	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	3	10000	1	1	0	2610	1	71	1	1	69817	30003	13	13	13	10000	30100	70055	70055	70036	70055	70055
40204	70054	524	0	0	0	0	0	0	1	0	0	0	0	70039	69785	59714	25	40104	30103	10001	30100	10000	616041	3342398	1	49	66974	70051	70054	64647	3	64957	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69873	30003	10	10	10	10000	30100	70036	70100	70062	70052	70052
40204	70051	525	0	0	0	0	0	0	1	0	0	1	0	70020	69785	59695	25	40104	30103	10000	30100	10000	616014	3342398	1	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69817	30003	10	10	13	10000	30100	70055	70055	70055	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	525	0	0	0	0	1	0	0	70036	69778	59710	25	40010	30013	10001	30010	10000	617018	3342398	0	0	49	66971	0	70054	70054	64672	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	0	0	2	71	1	1	69798	30000	13	10	0	10000	30010	70036	70052	70055	70036	70055
40024	70054	525	0	0	0	0	1	1	0	70039	69743	59713	25	40014	30013	10001	30010	10000	617018	3342398	0	0	49	66974	0	70035	70035	64672	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	2520	0	0	1	71	1	1	69817	30003	13	13	10	10000	30010	70052	70052	70055	70055	70052
40024	70035	525	0	0	0	0	1	1	0	70039	69778	59710	25	40010	30010	10000	30010	10000	617018	3342398	0	0	49	66955	0	70054	70035	64669	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	2326	10000	1	1	0	2520	0	0	1	71	1	1	69798	30003	13	0	0	10000	30010	70055	70058	70038	70036	70036
40024	70035	524	0	0	0	0	1	1	0	70039	69778	59713	25	40014	30013	10001	30010	10000	617018	3342398	0	0	49	66974	0	70054	70054	64672	3	65022	40010	30020	10000	60020	20000	70059	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	5	1	2	71	1	1	69817	30000	0	0	0	10000	30010	70052	70036	70055	70055	70036
40024	70035	525	0	0	0	0	1	1	0	70020	69775	59713	25	40014	30021	10001	30010	10000	616991	3342254	0	0	49	66955	0	70054	70051	64653	3	65037	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	0	0	1	71	2	1	69817	30003	14	0	13	10000	30010	70055	70036	70052	70055	70036
40024	70054	524	0	0	0	0	0	1	0	70039	69778	59713	25	40014	30013	10000	30010	10000	616991	3341470	0	0	49	66955	0	70054	70054	64672	3	64960	40010	30020	10000	60020	20000	70059	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	0	0	1	71	1	1	69798	30003	10	10	13	10000	30010	70052	70052	70052	70036	70036
40024	70051	524	1	0	0	0	1	1	0	70036	69778	59713	25	40014	30013	10001	30010	10000	617018	3341470	0	0	49	66955	0	70051	70051	64672	3	65017	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	0	0	1	71	1	2	70040	30003	10	13	13	10000	30010	70052	70036	70052	70036	70036
40024	70051	525	0	0	0	0	1	0	0	70020	69775	59695	25	40010	30013	10001	30010	10000	617068	3342398	0	0	49	66974	0	70054	70035	64653	3	64963	40205	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10003	0	0	10000	1	1	0	2520	5	1	1	71	1	1	69817	30003	10	0	13	10000	30010	70052	70052	70036	70036	70055
40024	70035	525	0	0	0	0	0	0	0	70039	69775	59695	25	40014	30013	10001	30010	10000	617018	3341470	1	5	49	66955	0	70054	70054	64672	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	0	0	2520	5	1	1	71	1	1	69817	30003	13	0	13	10000	30010	70052	70055	70036	70036	70052
40024	70051	524	0	0	0	0	1	0	0	70020	69775	59710	25	40014	30010	10000	30010	10000	617068	3342398	0	0	49	66971	0	70054	70054	64653	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	0	0	2520	0	0	1	71	1	1	69817	30000	13	10	13	10000	30010	70036	70036	70055	70055	70036

Test 4: throughput

Count: 8

Code:

  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26737	200	0	1	0	1	0	0	0	0	0	21	0	1	26722	2	12	0	16	25	80100	100	80000	100	80015	500	1167628	0	49	23634	26736	26737	16642	6	16688	80115	200	80024	200	160048	26736	64	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	43	80059	1	0	0	61	80000	6	1	60	43	19	1	1	1	1	5118	1	16	1	1	26733	10	0	7	80000	100	26732	26732	26732	26732	26732
80204	26707	200	0	1	0	1	0	0	0	0	0	44	0	1	26877	2	1	1	19	25	80100	100	80000	100	80015	500	1160520	0	49	23634	26736	26736	16663	6	16689	80116	200	80024	200	160048	26714	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	38	80038	6	1	39	44	0	0	1	1	1	5118	1	16	1	1	26728	0	14	7	80000	100	26732	26732	26728	26732	26708
80204	26731	200	0	1	0	1	0	0	0	0	0	44	0	1	26893	0	1	0	19	25	80100	100	80000	100	80013	500	1166795	0	49	23656	26714	26736	16642	6	16666	80116	200	80024	200	160048	26737	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80038	0	0	0	0	80038	6	1	0	0	0	0	1	1	1	5118	1	16	1	1	26728	10	10	0	80000	100	26717	26739	26734	26741	26732
80204	26707	200	0	1	0	1	0	0	0	0	0	0	0	1	26698	2	1	1	19	25	80100	100	80000	100	80015	500	1167215	0	49	23634	26714	26714	16664	6	16688	80113	200	80024	200	160048	26714	85	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80038	0	1	1	38	80040	6	0	0	44	0	0	1	1	1	5118	1	16	1	1	26728	14	0	7	80000	100	26732	26732	26728	26732	26732
80204	26731	200	0	1	0	1	0	0	0	0	0	44	0	1	26876	2	1	0	0	25	80100	100	80000	100	80015	500	1167303	0	49	23651	26727	26731	16635	6	16659	80115	200	80024	200	160048	26734	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	0	0	0	80038	6	1	54	44	0	0	1	1	1	5118	1	16	1	1	26704	14	14	4	80000	100	26732	26708	26708	26732	26708
80204	26707	200	0	1	0	1	0	0	0	0	0	0	0	1	26716	2	0	12	0	25	80100	100	80000	100	80015	500	1169949	0	49	23656	26737	26736	16664	6	16688	80115	200	80024	200	160048	26737	85	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	43	80038	0	0	0	0	80039	0	1	38	44	0	0	1	1	1	5118	1	16	1	1	26704	10	10	4	80000	100	26708	26732	26708	26732	26708
80204	26731	200	0	1	0	1	0	0	0	0	0	69	0	0	26885	2	12	12	19	25	80100	100	80000	100	80015	500	1169949	0	49	23656	26714	26736	16664	6	16666	80113	200	80024	200	160048	26737	64	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80000	0	0	0	39	80038	0	1	38	44	0	0	1	1	1	5118	1	16	1	1	26728	14	14	4	80000	100	26732	26732	26732	26708	26732
80204	26731	200	0	1	0	1	0	0	0	0	0	44	0	0	26737	2	1	1	16	25	80100	100	80000	100	80016	500	1167377	0	49	23657	26736	26736	16642	6	16665	80112	200	80024	200	160048	26736	86	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	0	0	0	80038	0	1	38	44	0	0	1	1	1	5118	1	16	1	1	26728	10	14	0	80000	100	26732	26737	26715	26732	26732
80204	26731	200	0	1	0	1	0	0	0	0	0	44	0	1	26848	2	0	1	19	25	80100	100	80000	100	80015	500	1167215	0	49	23634	26736	26737	16664	6	16688	80115	200	80024	200	160048	26736	64	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	43	80038	0	0	0	3	80039	6	1	38	44	0	0	1	1	1	5118	1	16	1	1	26728	14	10	4	80000	100	26728	26728	26728	26728	26732
80204	26731	200	0	1	0	1	0	0	0	0	0	44	0	1	26900	2	0	12	16	25	80100	100	80000	100	80015	500	1167215	0	49	23656	26737	26736	16664	6	16688	80115	200	80024	200	160048	26714	85	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	43	80038	0	0	0	38	80038	0	1	38	0	0	0	1	1	1	5118	1	16	1	1	26704	0	14	0	80000	100	26728	26732	26728	26728	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26723	200	0	0	1	0	315	0	0	0	2	26693	2	12	12	0	25	80010	10	80000	10	80000	50	1172240	1	49	23628	26727	26708	16667	3	16783	80010	20	80000	20	160000	26722	72	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	39	80000	0	0	35	80039	6	1	35	39	5020	0	18	16	0	14	16	26705	0	6	0	80000	10	26728	26728	26712	26723	26728
80024	26708	200	0	0	0	0	300	0	1	0	2	26712	0	12	12	12	25	80010	10	80000	10	80000	50	1168843	1	49	23642	26708	26727	16672	3	16713	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80000	0	0	0	80035	6	1	35	39	5020	0	17	16	0	17	17	26724	10	6	4	80000	10	26709	26723	26729	26728	26709
80024	26722	200	0	0	0	0	381	0	0	0	0	26693	2	12	0	0	25	80010	10	80000	10	80000	50	1166886	0	49	23642	26728	26728	16672	3	16707	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80035	0	0	0	80039	6	1	39	43	5020	0	17	16	0	17	16	26725	10	10	4	80000	10	26709	26723	26723	26728	26723
80024	26728	200	0	0	0	0	273	0	1	0	0	26712	2	0	18	16	25	80010	10	80000	10	80000	50	1172240	1	49	23628	26708	26727	16672	3	16708	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80035	0	0	39	80039	6	1	0	43	5020	0	17	16	0	9	17	26724	0	10	4	80000	10	26709	26728	26723	26728	26729
80024	26728	200	0	0	0	0	312	0	1	0	2	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1166886	0	98	23628	26728	26708	16672	3	16786	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80035	0	0	35	80000	6	1	39	0	5020	0	14	16	0	17	14	26705	10	10	4	80000	10	26729	26728	26723	26709	26729
80024	26722	200	0	0	0	0	281	0	1	0	2	26707	2	0	12	2	25	80010	10	80000	10	80000	50	1166750	0	49	23628	26727	26727	16652	3	16709	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80000	0	0	35	80000	6	1	35	39	5020	0	17	16	0	17	17	26705	0	0	0	80000	10	26729	26729	26709	26728	26728
80024	26708	200	0	0	0	0	282	0	1	0	0	26693	2	12	0	16	25	80010	10	80000	10	80000	50	1166750	0	49	23642	26722	26722	16672	3	16715	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80000	0	0	0	80000	6	1	35	39	5020	0	9	16	0	17	14	26705	6	6	0	80000	10	26723	26723	26723	26723	26723
80024	26708	200	0	0	0	0	306	0	1	0	0	26712	2	0	12	12	25	80010	10	80000	10	80000	50	1166750	0	49	23647	26728	26708	16672	3	16693	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80000	0	0	0	80036	6	1	35	43	5020	0	17	16	0	15	17	26724	10	6	0	80000	10	26709	26728	26709	26729	26728
80024	26727	200	0	0	1	0	311	0	0	0	2	26712	2	18	12	16	25	80010	10	80000	10	80000	50	1168843	0	49	23642	26722	26722	16667	3	16712	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	0	39	80039	6	0	0	0	5020	0	17	16	0	13	17	26728	10	10	4	80000	10	26723	26728	26709	26709	26729
80024	26708	200	0	0	0	1	45	0	1	0	0	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	0	49	23645	26722	26723	16667	3	16702	80010	20	80000	20	160000	26725	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80035	0	0	0	80000	6	1	35	39	5020	0	17	16	0	17	17	26719	6	6	2	80000	10	26723	26723	26709	26723	26723

LDR (register, sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations